Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Hsieh, E. R. | en_US |
dc.contributor.author | Chuang, C. H. | en_US |
dc.contributor.author | Chung, Steve S. | en_US |
dc.date.accessioned | 2017-04-21T06:49:09Z | - |
dc.date.available | 2017-04-21T06:49:09Z | - |
dc.date.issued | 2016 | en_US |
dc.identifier.isbn | 978-1-4673-9478-9 | en_US |
dc.identifier.issn | 1930-8868 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/136424 | - |
dc.description.abstract | For the first time, a new 1T1R of volatile memory based on the interfacial dipole flipping mechanism, named as Dipole Dynamic Random Access Memory (DiRAM), has been reported. It features 4ns per bit of dipole switching time, larger than 109 of endurance, and 10 seconds of retention with reasonable positive and negative resistance window, low operation voltages with bit line at 0.8V and word line at 0.2V, and around 1 nano-Watt per bit of operation power. DiRAM is also easy to be integrated with state-of-the-art CMOS technology. The results have shown that this volatile memory may be a potential candidate for the next generation DRAM technology. | en_US |
dc.language.iso | en_US | en_US |
dc.title | An Innovative 1T1R Dipole Dynamic Random Access Memory (DiRAM) featuring High Speed, Ultra-low power, and Low Voltage Operation | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2016 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATION (VLSI-TSA) | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000389022000017 | en_US |
dc.citation.woscount | 0 | en_US |
Appears in Collections: | Conferences Paper |