Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Yu, Chang-Hung | en_US |
| dc.contributor.author | Su, Pin | en_US |
| dc.contributor.author | Chuang, Ching-Te | en_US |
| dc.date.accessioned | 2017-04-21T06:49:25Z | - |
| dc.date.available | 2017-04-21T06:49:25Z | - |
| dc.date.issued | 2016 | en_US |
| dc.identifier.isbn | 978-1-4673-9478-9 | en_US |
| dc.identifier.issn | 1930-8868 | en_US |
| dc.identifier.uri | http://hdl.handle.net/11536/136434 | - |
| dc.language.iso | en_US | en_US |
| dc.title | Performance Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits | en_US |
| dc.type | Proceedings Paper | en_US |
| dc.identifier.journal | 2016 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATION (VLSI-TSA) | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.identifier.wosnumber | WOS:000389022000041 | en_US |
| dc.citation.woscount | 0 | en_US |
| Appears in Collections: | Conferences Paper | |
- Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits and 6T SRAM Cells / Yu, Chang-Hung;Su, Pin;Chuang, Ching-Te
- Performance and Stability Benchmarking of Monolithic 3-D Logic Circuits and SRAM Cells With Monolayer and Few-Layer Transition Metal Dichalcogenide MOSFETs / Yu, Chang-Hung;Su, Pin;Chuang, Ching-Te
- Performance Evaluation of Pass-Transistor-Based Circuits using Monolayer and Bilayer 2-D Transition Metal Dichalcogenide (TMD) MOSFETs for 5.9nm Node / Yu, Chang-Hung;Zheng, Jun-Teng;Su, Pin;Chuang, Ching-Te
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