Performance Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Yu, Chang-Hung	en_US
dc.contributor.author	Su, Pin	en_US
dc.contributor.author	Chuang, Ching-Te	en_US
dc.date.accessioned	2017-04-21T06:49:25Z	-
dc.date.available	2017-04-21T06:49:25Z	-
dc.date.issued	2016	en_US
dc.identifier.isbn	978-1-4673-9478-9	en_US
dc.identifier.issn	1930-8868	en_US
dc.identifier.uri	http://hdl.handle.net/11536/136434	-
dc.language.iso	en_US	en_US
dc.title	Performance Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	2016 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATION (VLSI-TSA)	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000389022000041	en_US
dc.citation.woscount	0	en_US
顯示於類別：	會議論文