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dc.contributor.authorChou, MFen_US
dc.contributor.authorWen, KAen_US
dc.contributor.authorChang, CYen_US
dc.date.accessioned2014-12-08T15:19:02Z-
dc.date.available2014-12-08T15:19:02Z-
dc.date.issued2005-06-01en_US
dc.identifier.issn0916-8524en_US
dc.identifier.urihttp://dx.doi.org/10.1093/ietele/e88-c.6.1280en_US
dc.identifier.urihttp://hdl.handle.net/11536/13671-
dc.description.abstractThis paper presents a dual-band mixer equipped with a dual-band load using current combine technique to minimize chip area by sharing inductors for each frequency band. A systematic design methodology for the current combine load based on parasitic effect considerations is also developed. By following the proposed design procedure, the load inductance and combine capacitance for the dual-band mixer can be easily determined. A 2.4/5.2-GHz CMOS mixer design has been implemented to demonstrate the feasibility of the design technique.en_US
dc.language.isoen_USen_US
dc.subjectdual-band mixeren_US
dc.subjectcurrent combineen_US
dc.titleDual-band mixer designen_US
dc.typeArticleen_US
dc.identifier.doi10.1093/ietele/e88-c.6.1280en_US
dc.identifier.journalIEICE TRANSACTIONS ON ELECTRONICSen_US
dc.citation.volumeE88Cen_US
dc.citation.issue6en_US
dc.citation.spage1280en_US
dc.citation.epage1284en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000229824600028-
dc.citation.woscount0-
Appears in Collections:Articles