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dc.contributor.authorLi, YMen_US
dc.contributor.authorYu, SMen_US
dc.contributor.authorLee, JWen_US
dc.date.accessioned2014-12-08T15:19:23Z-
dc.date.available2014-12-08T15:19:23Z-
dc.date.issued2005-04-01en_US
dc.identifier.issn0021-4922en_US
dc.identifier.urihttp://dx.doi.org/10.1143/JJAP.44.2132en_US
dc.identifier.urihttp://hdl.handle.net/11536/13839-
dc.description.abstractIn this paper we present a quantum mechanical corrected gate tunneling current model for simulating ultrathin oxide metal-oxide-semiconductor (MOS) devices. By approximating the physically based Esaki-Tsu tunneling formula and explicitly modeling the classical (CL) and quantum mechanical (QM) corrected surface potential, this model successfully predicts the gate tunneling current for ultrathin oxide MOS samples under different applied biases. Simply assuming all tunneling electrons have the same kinetic energy, the Esaki-Tsu tunneling formula is first simplified so that it can be solved without encountering numerical integral. problems. Numerical solutions of the classical Poisson equation and Schrodinger-Poisson equations are then used to analytically express the CL and QM corrected surface potentials explicitly in terms of substrate doping, thickness of the gate oxide (T(ox)(ox)(), and applied bias. The full explicit, physical-based, and QM corrected gate tunneling current model quantitatively shows good agreement with the technology computer-aided design (TCAD) simulation. Compared with the measured gate tunneling current from fabricated 0.12 mm n-type Metal-Oxide-Semiconductor Field Effect Transistors (NMOSFETs) with three different thicknesses of gate oxide, T) = 1, 1.2 and 1.5 nm, the QM corrected gate tunneling current model shows good accuracy for various ultrathin oxide samples under different biases. However, the gate tunneling current model with the CL surface potential results in one order of magnitude underestimation in comparison with the measured data. We implement the gate tunneling current model into the simulation program with integrated circuit emphasis (SPICE) simulator and perform a DC simulation. Simulated results preliminarily show the effect of the gate leakage current on the drain current without any numerical convergence problem.en_US
dc.language.isoen_USen_US
dc.subjectgate tunneling currenten_US
dc.subjectcompact modelen_US
dc.subjectEsaki-Tsu formulaen_US
dc.subjectphysical-based explicit classical surface potential quantum mechanical corrected surface potentialen_US
dc.subjectSPICEen_US
dc.subjectultrathin oxide MOSFETen_US
dc.subjectDC characteristicsen_US
dc.subjectdevice modelingen_US
dc.subjectcircuit simulationen_US
dc.titleQuantum mechanical corrected simulation program with integrated circuit emphasis model for simulation of ultrathin oxide metal-oxide-semiconductor field effect transistor gate tunneling currenten_US
dc.typeArticleen_US
dc.identifier.doi10.1143/JJAP.44.2132en_US
dc.identifier.journalJAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERSen_US
dc.citation.volume44en_US
dc.citation.issue4Ben_US
dc.citation.spage2132en_US
dc.citation.epage2136en_US
dc.contributor.department友訊交大聯合研發中心zh_TW
dc.contributor.departmentD Link NCTU Joint Res Ctren_US
dc.identifier.wosnumberWOS:000229095700010-
dc.citation.woscount3-
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