用負載拉移觀察SiGe HBT增益壓縮機制與低損耗閘極電感雙頻低雜訊放大器

Abstract

本論文主要分成兩個位於射頻前端收發器的重要電路進行研究，分別為功率放大器與低雜訊放大器，首先對於功率放大器部分，我們針對TSMC 0.18-μm SiGe BiCMOS的高壓操作功率元件利用負載拉移(Load Pull)來量測功率輸出特性，針對不同偏壓操作與用負載拉移量測得到的等功率軌跡圖尋找不同輸出阻抗的匹配，也就是在RHi與RLO情況下對輸出特性造成的影響，我們觀察在接近增益壓縮1dB的位置時電流的變化情形，並判斷於不同偏壓操作時所造成的增益壓縮機制，並當選擇不同負載阻抗時，也會受到其他偏壓的增益壓縮影響，了解其操作特性將有助於我們設計功率放大器的方法。 接著針對雙頻帶功率放大器利用在限制輸出功率下對於輸入與雜訊同時匹配的設計方法，進行最佳化設計的說明與電路實現步驟，但對於使用非理想元件時，最低雜訊指數會受到LC共振腔匹配而改變，使得雙頻帶的中間有突起的雜訊，因此如何改善雜訊指數也成為本論文研究重點，在雙頻低雜訊放大器2.4/5.2GHz的設計，我們利用微機電(MEMS)製程整合0.18-μm CMOS、利用有無打線電感在0.18-μm SiGe BiCMOS比較，第三個再利用0.11μm CMOS高基板電阻特性來實現，主要目的是為了降低電感的損耗，讓整體電路雜訊指數降低，最後以0.11-μm CMOS設計2.4GHz單頻低雜訊放大器設計，來說明設計最佳化的取捨關係，並討論其結果。

This thesis studies two important circuits in RF front-end, including power amplifiers (PAs) and low-noise amplifiers (LNAs). This thesis introduces power performance of PAs. We use Load Pull system to measure some high voltage power devices using TSMC 0.18μm SiGe BiCMOS technology. By Observing the change of currents near P1dB for different bias points and for different output impedances (RHi、RLO) based on Load Pull contours, we can judge what gain compression mechanism happens for any specific bias point. When choosing different load impedance, the device will experience other gain compression mechanism. Therefore, knowing these operation characteristics help us design PA easily and know power devices’ limitations. On the other hand, we use the method of power constrained simultaneously noise and input match to optimize the dual band (2.4/5.2GHz) low noise amplifier. Besides, the analysis of optimization and design flow of a dual band LNA are illustrated in this thesis. However, the noise figure minimum (NFmin) changes when using none-ideal components, especially the input LC-tank. It causes a noise spike (resonant frequency) between two operating bands. As a result, how to improve noise figure is one of the important things in this thesis. We use three different technologies and methods to reduce the impact of non-ideal inductors to suppress loss brought by inductors and make noise figure lower. This thesis demonstrates three 2.4/5.2 GHz concurrent dual-band LNAs using MEMS integrating 0.18-μm CMOS, 0.18-μm SiGe BiCMOS wi/wo bondwire inductor and 0.11-μm CMOS (high resistive substrate), respectively. All of these doings are to reduce the impact by non-ideal inductors, especially LC-tank. Finally, the thesis demonstrates two single band 2.4-GHz LNAs using 0.11 μm CMOS to show its design trade-off. This claimed noise optimization design method is demonstrated and finally discussed through the measurement results.