可利用石墨烯最佳化金半接面歐姆接觸之特性研究

Abstract

由發展至今的半導體製程技術中得知，為了降低線路RC delay，金屬內部連線部分已由原先的鋁轉成銅製程，因銅具有相對較低的電阻，但缺點是銅在介電層氧化矽中更容易擴散，因此在介面加上阻擋層(Ta/TaN)使銅不易擴散至介電層中，但阻擋層的使用會使得線寬微縮製程增加困難度。為了改善這個問題，可將石墨烯應用在氧化矽及銅之間作為阻擋層，也可以進一步降低整體連線電阻，因此本研究中將以石墨烯，作為銅阻擋層應用在半導體製程中，進而提升元件之歐姆接觸。 由於石墨烯的低載子濃度會限制電流的穩定性，利用電鍍銅在石墨烯表面，相當於並聯銅與石墨烯，且可以藉由銅提供石墨烯載子，有效降低電阻達到更高導電度。本研究藉由微影的技術，利用光阻在石墨稀上定義出需要的圖形，再電鍍銅上去，此時的銅只會電鍍在我們定義的圖形上，接著進行氧氣電漿蝕刻不需要的石墨烯，形成特定形狀。因製程簡單，並可以定圖案化石墨烯，並且石墨烯可以有效阻擋銅擴散，若將此技術應用在接觸電阻上，有希望有希望併入傳統銅製程方式，達到更低接觸電阻以及阻擋層的效用。

In order to reduce the RC delay in logic device, copper wire had replaced Al wire in current interconnect process. Copper is a relative low resistivity material, but it’s easily to diffuse in dielectric silicon oxide layer. Therefore, using Ta/TaN as diffusion barrier is necessary. However, an additional barrier layer will increase the difficulty to device downscale. We use graphene to replace the Ta/TaN as the diffusion barrier in copper interconnect, and it will reduce the total resistivity. Combining graphene into contact electrode will improve the electrical characteristics for the goal of ohmic contact in between graphene and silicon. Due to graphene’s low carrier concentration limiting the current sustainability, we use electroplating copper onto graphene to increase the carrier concentration and enhance conductivity. Furthermore, we can use lithography to make the graphene patterning, and removing the residual graphene by oxygen plasma etching. This is a simple and compatible method in nowadays semiconductor industry. Graphene as alternative material in interconnect is prospective in the future