前瞻式金氧半場效電晶體之隨機電報訊號分析與熱載子劣化研究

Abstract

在CMOS技術的演進，近年來分為兩個方向，第一個方向為延續Moore定律，持續地在元件尺寸方面進行微縮(More Moore)，另一方向則是在於增加功能的多樣性，將不同功能之元件，從原本於主機板做整合，轉由在封裝或是晶片階段時做整合，稱為More than Moore。在More Moore部分，隨著CMOS元件尺寸的微縮，在通道中，單顆載子對元件特性的影響越來越明顯，隨機電報訊號(Random Telegraph Signal, RTS)則是元件中的缺陷，捕捉/放射通道中的單顆或數顆載子，並進一步影響元件電性的結果。由於當元件持續在微縮時，RTS對於電性的影響比例逐漸增加，近年來成為研究的主流題目。另外，在More than Moore的發展部分，其包含了眾多不同功能的元件，如RF、高壓元件、CMOS image sensor等，而在高壓元件部分，因為其操作偏壓較高，在熱載子的可靠度部分則是研究重點。 因此我們在第一部分主要利用汲極電流的RTS(ID-RTS)，對partially-depleted的silicon-on-insulator(PD SOI)元件中的缺陷之物理位置進行研究。首先，在閘極氧化層厚度約為1奈米的元件，因為反轉層的量子效應對於等效氧化層厚度的貢獻越顯重要，所以在萃取缺陷的垂直位置時，須先計算出最高的反轉電子濃度距離SiO2與Si的位置，之後，將此距離考慮至等效氧化層厚度中，並利用平均捕捉時間與平均放射時間的比例(<c>/<e>)對閘極電壓(VG)的線性斜率，得到氧化層缺陷距離SiO2與Si介面為4 Å。在另一個氧化層厚度為10 nm之元件中，我們觀察到在介於弱反轉與強反轉區之間的中度反轉區有明顯兩階的ID-RTS，先藉由不同的汲極電壓與溫度下的汲極電流分析，確認出RTS對應的汲極電流為擴散電流主導，由於在擴散電流下，靠近源極與汲極端的通道電位分別只對源極與汲極電壓有明顯相關性，之後利用此特性以及交換通道左右兩邊電壓和Shockley-Read-Hall (SRH) model，比較載子捕捉時間以及對應的電流變化量，會觀察到載子捕捉時間以及電流變化量，當橫向電壓施加在源極端時會較高，並且載子捕捉時間僅對源極電壓有正相關的關係，因此可得到缺陷的橫向位置為靠近源極端。另外，當VG從中度反轉區增加至強反轉區時，觀察到兩階的ID-RTS變為三階的ID-RTS，在這邊我們提出一個新的分析方式，藉由在交換通道左右兩邊電壓前後，於第二階的平均時間隨VG的變化，進一步得到對應的兩個缺陷橫向位置的座落區域，並且，缺陷的座落區域也可透過基於SRH model的計算來證實。 第二部分則是在high-k/metal gate元件中的ID-RTS研究，首先利用<c>/<e>對VG的線性斜率，得到在兩個元件中的缺陷，分別位於HfO2中以及在HfO2和SiO2的介面。之後利用不同溫度下的ID-RTS以及先前文獻的相關公式，得到缺陷的數種物理特性，包含缺陷的捕捉與放射的活化能(ECT與EB)、缺陷放射出載子前後之熵的變化量(S)、以及在缺陷捕捉/放射載子的過程中藉由多聲子放射理論(multiphonon emission theory)得到的晶格鬆弛能量(Erelax)。而我們觀察到這些物理特性隨VG的變化不同於以往在相同萃取方式下，使用傳統二氧化矽作為氧化層的元件所得到的結果。在S部分，其VG的相關性主要是在HfO2中，被捕獲之電子在越大的閘極電壓越不易放射至反轉通道中，進而使S與閘極電壓成反相關性。另外，在EB與Erelax部分，與傳統元件中的差異主要來自於HfO2層中所主導的氧化層缺陷(氧空缺)，其晶格震盪模式會因HfO2中，不同的Fermi-level位置(對應不同的VG)而改變，因此，根據multiphonon emission theory，我們會觀察到Erelax與EB隨VG有不同的變化，這部分我們也利用兩個不同的high-k元件(HfO2和Hf1-xZrxO2)來驗證這些物理特性隨VG的變化機制。 最後，在高壓元件p型雙擴散汲極(Double Diffused Drain, DDD) MOSFETs部分，其元件於熱載子裂化實驗後，有從源極流至汲極的漏電流(off-current)，但是元件的基本特性，如臨界電壓與次臨界擺幅並無明顯的變動，而藉由IV特性與不同接法的charge pumping量測，得知主要的裂化區域位在汲極端的閘極與p型DDD重疊區域。在off-current的產生機制部分，由於off-current與熱載子裂化實驗中的n型井之逆偏壓有正相關性，並且透過ISE-TCAD的3D元件電場分佈模擬，得知在汲極端的淺溝渠隔離(shallow trench isolation, STI)邊緣之電場比在通道中央的強，另外，在STI內有一層薄SiN存在，所以推測off-current的產生，是因靠近STI的汲極端表面較強之電場，產生出較多或較高能量之電子，其後受到汲極端與n型井之間強電場(ED,BULK)影響，加速至底下的n型井區域，而經由ED,BULK加速而得到能量的電子，因為其位置較接近STI(即在通道寬度方向的兩側)，具較高能量的電子就有機會被捕捉至STI的SiN層中，並且，因為ED,BULK的方向有部分指向源極端，使電子捕捉的情況會從汲極端往源極端延伸，進而在表面電流底下形成off-current的路徑。之後，我們利用ISE-TCAD的3D元件電性模擬以及不對稱元件結構，驗證off-current路徑是在距離表面最大空乏區以外之處。另外，也利用裂化前後在不同接法的charge pumping電流比較，驗證off-current路徑的形成，並且，透過不同STI製程的元件，驗證STI中的SiN層為off-current產生的來源。

Recently, there are two directions for the revolution of CMOS technology. The first one is called “More Moore” which is the continuous scaling down of the device for extending Moore’s law. The other way is the enhancement of the functional diversification which is called “More than Moore”. In “More than Moore”, it allows the integration of functionalities to migrate from system board-level to package-level or chip-level. With the development of the scaling down, the impact of discrete channel carrier on device performance becomes more apparent. The Random Telegraph Signal (RTS) phenomenon is commonly related to the behaviors of one or some carriers that have been captured and emitted by the oxide traps and then causes the variation of electrical characteristics. Because the impact of RTS on electrical characteristics is more important when the device is scaled down, RTS have become a mainline research topic. On the other hand, in the development of “More than Moore”, it includes many kinds of device, such as RF, high-voltage, and CMOS image sensor. As for the high-voltage devices, because the operation voltage is higher, the reliability of hot carrier is the key of the research. Therefore, the main body in this dissertation begins with the investigation of the physical position of the trap according to drain current RTS (ID-RTS) in the partially-depleted silicon-on-insulator (PD SOI) MOSFETs. First, when the thickness of gate oxide is scaled down to about 1 nm, the contribution of inversion thickness, resulted from quantization effect, to the effective oxide thickness becomes more important. Therefore, to extract the vertical position of the trap, it needs to calculate the distance between the maximum inversion concentrations of electron and the SiO2/Si interface. And then, incorporating this distance into the effective oxide thickness and using the linear slope of average capture time/average emission time (<c>/<e>) versus gate voltage (VG), the oxide trap is determined to be at the 4 Å with respect to the SiO2/Si interface. In another PD SOI device with the oxide thickness of 10 nm, we observed that there is an apparent two-level ID-RTS located in the moderate inversion region which is between weak and strong inversion regions. According to the analysis of drain current (ID) at different drain voltages (VD) and temperatures, the dominating transport mechanism of ID in the RTS observation region is demonstrated to be the diffusion current. In the diffusion current-dominated region, the application of drain (source) voltage will influence the channel potential at the drain (source) side only. Then, using this property, the measurement with and without interchanged voltage at source and drain sides, and Shockley-Read-Hall (SRH) model, it can compare the capture time of carrier (<c>) and the relative amplitude of channel current (I/I) for further study. In this work, it shows that <c> andI/I are larger when the voltage is applied at source side (VS), and <c> only increases with VS. Thus, the trap position is determined to be near the source side. Moreover, when VG increases from moderate inversion region into strong inversion, the two-level ID-RTS changes to three-level ID-RTS. Here, we proposed a new analyzed method that is comparing the VG dependence of the average time at the second level under the ID-RTS measurement with and without interchanged voltage at source and drain sides to acquire the located region of lateral position for the corresponding two traps. Furthermore, these positions are confirmed by the calculation based on SRH model. In the second part, it focuses on the investigation of ID-RTS in high-k/metal gate MOSFETs. Using the linear slope of <c>/<e> versus VG, the vertical position of trap in two devices are determined to be in HfO2 and at HfO2/SiO2 interface. Then, according to ID-RTS at different temperatures and the corresponding equations in the previous studies, it can obtain some physical characteristics of trap including the energy barrier height for capturing the channel carrier (EB), trap binding energy (ECT), change in entropy when the trapped electron is emitted into channel (S), and lattice relaxation energy based on the multiphonon emission theory (Erelax). After these extractions, we observed that the VG dependencies of these characteristics are different from those based on the same extracting method in conventional devices with SiO2-based gate oxide. In part of S, its VG dependence results from the fact that the trapped electron in HfO2 will be emitted into inversion channel with more difficulty when VG increases. Therefore, S decreases with VG. On the other hand, as for EB and ECT, because the lattice vibration mode of oxygen vacancy which is the main defect in HfO2 will be influenced by the position of Fermi-level with respect to valence band in HfO2 (corresponding to different VG), EB and ECT show the different VG dependencies from those in SiO2-based MOSFETs according to the multiphonon emission theory. Moreover, the mechanisms for these VG dependencies of characteristics are confirmed by comparisons between two HfO2-based devices (HfO2 and Hf1−xZrxO2). Finally, in high-voltage devices, here, we used p-channel double diffused drain (DDD) MOSFETs, there is an apparent off-current flowed from source to drain after the experiment of hot carrier degradation. However, the basic properties of the device such as threshold voltage and subthreshold swing almost unchanged after stress. According to the analysis of I-V characteristics and charge pumping measurement at different configurations, the main degraded region is at the overlap region between gate and p-type DDD at drain side. As for the mechanism of off-current generation, the value of the off-current is proportional to the reverse voltage at n-well. Furthermore, according to the electric field distribution in 3D device by ISE-TCAD simulation, the electric field at the drain-side corners on the shallow trench isolation (STI) edge is larger than that in center of the channel in width direction. Moreover, there is a thin SiN layer in STI. Therefore, the more electrons or the high-energy electrons generated by impact ionization at STI edge due to the existence of the higher electric field. And then, these electrons will be accelerated into the deeper region of n-well by the strong electric field in the depletion region between drain and n-well (ED,BULK). Because these hot electrons are near STI (namely, on the two sides of channel in width direction), they can be easily trapped in the SiN layer in STI. Furthermore, the vector component of ED,BULK directs to source. Therefore, the sequence of electron trapping in STI will extend from drain to source and then the conductive path for off-current is formed below the main channel current. After that, we use the simulation of electric property in 3D device by ISE-TCAD and the device with asymmetric structure to confirm that the depth of the path for off-current is beyond the maximum depletion region. Besides, the path formation for off-current is further demonstrated by the comparison of charge pumping current at different configurations between initial state and after stress. Moreover, according to the comparisons of the experimental results at the devices with different STI fabrication processes, it confirms that the SiN layer in STI is the origin of the off-current.