結合資料探勘與密度估計分析的電壓雜訊感測器擺置演算法

Abstract

在現代將晶片操作於近臨界電壓計算的技術下，電壓緊急狀況正在非常嚴重地威脅著晶片的電壓雜訊邊界，因此電壓雜訊感測器被安插到晶片裡以避免晶片在運行時發生多變的電壓真實性議題，在這篇論文中，我們使用了一種基於關聯式法則探勘的技術來規劃及擺置電壓雜訊感測器，這個方法可以考量到電壓雜訊感測器的失誤率(任一節點發生電壓緊急狀況且電壓雜訊感測器沒有偵測到電壓緊急狀況的機率) 且同時最小化所需要使用的電壓雜訊感測器數目，實驗結果顯示我們的方法在以最少的感測器數目來收歛感測器失誤率至零是非常有效的，與最新的擺置技術相比，我們的方法在測試資料中均能使用少於最新擺置技術一半以上的電壓雜訊感測器數目，並且達到可以互相比擬甚至是更小的失誤率。

Due to near-threshold computing nowadays, voltage emergency is threatening our design margins very seriously. Noise sensors are inserted in order to prevent various integrity issues from happening during runtime. In this thesis, we use a new technique based on association rule mining to plan and place noise sensors. This new methodology can consider the miss rate (the probability of any node occurring voltage emergency without any detection by placed sensors) and simultaneously minimize the number of sensors utilized. The results show that our approach is very effective in converging the miss rate to zero by the least number of sensors. Compared with the state-of-the-art, we can reduce the number of sensors by half in benchmarks while the miss rate is comparable or even smaller than the prior work.