ECID：基於暫存器的EtherCAT系統辨識機制

Abstract

EtherCAT通訊系統是目前機器手臂控制系統的核心技術之一，透過最佳化資料的傳輸速度與頻寬，進而達到即時控制的目的。然而，EtherCAT通訊系統仍然存在著許多非理想性的因素，包括封包傳送週期的限制和時序抖動量，這些影響會讓工程師在鑑別伺服馬達的轉動慣量或摩擦係數的同時產生不準確性，因此，我們需要為工程師對EtherCAT通訊系統做系統辨識。在本論文中，我們提出一個方法，ECID，針對EtherCAT通訊系統的系統辨識方法。透過本論文所提出的方法，ECID可以藉由分佈時鐘暫存器（DC registers）的值來估測出系統時間差異（System time difference）、封包繞行時間（Packet traveling time）和時序抖動量（Clock cycle jitter）等應變變因。本論文也依這些變因找出EtherCAT通訊系統的特性，包括封包傳送週期的上下界，以及時序抖動量的標準差與系統負載之間變化的響應關係，稱為負載響應（Load response）。另外，ECID提供了一個數學模型用來描述封包傳送週期的值域和時序抖動量的機率分佈，如此一來，工程師便能藉由此數學模型來得知其EtherCAT通訊系統的行為表現。我們透過多項實驗來驗證ECID所估測出來的應變變因的可靠度。在系統時間差異的估測當中，ECID能夠透過系統時間差異的表現去區分出異質性的系統和同質性的系統。在封包繞行時間的估測當中，ECID能夠比實體量測儀器還要更準確的估測出封包繞行時間。在時序抖動量的估測中，ECID所估測出的時序抖動量包含了來自於主站、網路和從站裝置所產生的干擾。

The communication between a control application and servo motors requires high bandwidth and precise time determinism. To meet the requirements, EtherCAT is adopted as the fieldbus communication protocol. However, there are still some imperfection existing in an EtherCAT communication system, including rated clock cycle and clock cycle jitter. These influences would cause inaccuracy when an engineer determines characteristics of servo motors such as the moment of inertia or the coefficient of friction. Thus, the real-time performance of an EtherCAT communication system should be identified. In this paper, we present an EtherCAT communication system identification, named ECID, to estimate system time difference, packet traveling time and clock cycle jitter by using DC registers. The system parameters including boundary of clock and load response are then to identify an EtherCAT communication system. A mathematical model is presented to describe the range of clock cycle and the probability distribution of clock cycle jitter. We verify the relibility of ECID by conducting several experiments. From the experiments, we conclude that 1) ECID can distinguish heterogeneous devices and homogeneous devices by observing the performance of system time difference. 2) ECID can better estimate the packet traveling time. 3) The clock cycle jitter estimated by ECID is from all interference in the whole system including the master, network and slave devices.