應用於太陽能再生能源具預知式脈波頻率調變之雙模式數位降壓器

Abstract

近年來，隨著穿戴式產品普及化，而太陽能挾其可永續利用且低汙染的特性，迅速成為延長電池使用時間的重要輔助能源，乃至為發展無電池系統中的替代能源。其可應用的範圍包括無線感測器、物聯網以及生醫電子元件。然而為了有效利用有限的太陽能，後端數位電路已廣泛運用低電壓低功耗技術，將電晶體操作於次臨界區。因此，發展低電壓且高效率的電源管理系統已成為目前的趨勢，藉此將太陽能儲電裝置所產生的不穩定電壓轉換為穩定的系統電壓。另外，系統也需在極輕負載時具備夠高的轉換效率，方可使後端電路在待機狀態時最小化能量的消耗，進而延長電池壽命。 本論文實現一個應用於太陽能再生能源之雙模式數位降壓器，最高轉換效率達90.2%，其輸入電壓設計在太陽能最大功率點0.55~0.7伏，而輸出電壓為0.35~0.5伏數位電路於次臨界導通區域下操作，有效的使用有限的太陽能再生能源。藉由結合數位脈波調變模式以及預知式頻率調變模式，使雙模式數位降壓器涵蓋從50奈安培到30毫安培之負載範圍且從300奈安培到30毫安培有75%以上的效率，亦即在此範圍內降壓器能提供超越相同轉換比下理想線性穩壓器所能提供的最高效率。除此之外，藉由所提出之預感知式頻率調變模式來取代傳統零電流偵測電路，先行計算出下橋功率電晶體開關時間，使用數位機制來減少功率損耗;與傳統方式相比，此架構俱極小的功率消耗，藉此提高系統在極輕載時的轉換效率，並於100奈安培的負載下，提供高出ISSCC作品15.1%的轉換效率。

With the popularity of wearable products, photovoltaic energy harvesting is an attractive method to develop battery-free systems or prolong battery life, such as wireless sensors, biomedical electronics, and the internet of things (IoT). To sustain normal operation with a limited power budget, low-power digital circuits operating in the near/sub-threshold region are widely used in such applications. Therefore, the design of a low-voltage high efficiency buck converter which converts the harvested energy to the regulated output is dispensable. On the top of that, the conversion efficiency under ultra-light load becomes significant to increase system standby time. In this work, a dual-mode digital buck converter for photovoltaic energy harvesting with a maximum conversion efficiency of 90.2% is proposed. The input voltage (VIN) is targeted at 0.55−1.0V to meet the maximum power point voltages of the photovoltaic cell. The output voltage (VOUT) ranges from 0.35−0.5V, so that near/sub-threshold CMOS digital circuits utilize photovoltaic energy effectively. By integrating digital pulse-width modulation (DPWM) and the proposed predetermined pulse-frequency modulation (PPFM) together, the dual-mode digital buck converter provides wide output range from 100nA to 30mA, while achieving more than 75% efficiency from 300nA to 30mA, that is, in this range the proposed converter provides a high conversion efficiency which is higher than ideal low dropout linear regulator’s under same conversion ratio. In addition, the proposed PPFM calculates the off-time of the power transistor in advance without any zero-current detection circuit, thus reducing the power budget in conventional PFM. Compared with the conventional approaches, the proposed method has a very little power consumption in order to improve the efficiency under ultra-light. Thus, the converter provides a 15.1% higher conversion efficiency than previous work.