完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | 陳維勝 | zh_TW |
dc.contributor.author | 陳添福 | zh_TW |
dc.contributor.author | Rizal, Tanjung | en_US |
dc.contributor.author | Chen, Tien-Fu | en_US |
dc.date.accessioned | 2018-01-24T07:37:55Z | - |
dc.date.available | 2018-01-24T07:37:55Z | - |
dc.date.issued | 2016 | en_US |
dc.identifier.uri | http://etd.lib.nctu.edu.tw/cdrfb3/record/nctu/#GT070356139 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/139334 | - |
dc.description.abstract | 在設計一項物聯網(IoT)裝置的時候,節能省電已經成為主要考量之一,特別是對於需要電池才能運作的設備,更需要考慮電能的消耗。為了改善電能的使用率並達到省電的目的,設計者必須從架構階層來評估功率消耗及電能的使用情況,並且知道如何在節能與效能之間作取捨。非對稱式處理器(如big.Little)能夠改善電能的使用效率並且已經應用於許多架構中。然而,這種非對稱式處理器需要一個功率評估的工具來驗證任務是否在合適的處理器上運作以達到最佳電能使用率。許多應用於低電壓物聯網裝置的微控制器含有省電模式的切換,藉此提高電能使用率或是節能省電。但是,選擇電源模式必須在省電及喚起系統所導致的代價之間作取捨。對於評估整體系統的電能使用率及節能省電的狀況而言,從休眠中喚起系統所帶來的代價是不可忽略的重要因素。然而現有的功率評估工具並無法評估喚起系統所導致的代價。 在本論文中,我們提出了一個用於低電壓物聯網架構中的功率評估平台,此平包含了處理器、記憶體、感測器及周邊硬體的功率消耗樣板,並將其整合為功率評估的函式庫,透過此函式庫函能夠針對低電壓之物聯網應用提供一種最適合此應用的架構。最後,我們對使用非對稱式處理器架構的物聯網應用進行了功率及電能的使用做分析,並提供節能省電的資訊及從不同睡眠模式中喚起帶來多少的代價。 | zh_TW |
dc.description.abstract | Energy efficiency has become very important requirement in designing IoT (internet of things) devices, especially devices that are powered by battery. Many methods have been used to improve the energy efficiency, such as asymmetric core architecture, DVFS or various power saving modes. Asymmetric cores have been implemented in many architecture to improve the energy efficiency in various range of tasks, but there needs a power evaluation to show a certain task will be energy efficient in certain core. Furthermore, many microcontrollers (MCU) used in low-voltage IoT devices includes various power modes to improve the energy efficiency and energy saving. Those power modes are a trade-off between energy saving and system-wakeup overhead. Existing power evaluation tools do not take the wakeup overhead into account which is very important in evaluating the overall energy efficiency or energy saving. In this thesis, we propose a power evaluation platform for low-voltage IoT architecture. This power platform consisted of core power model, memory power model, and sensors/peripherals power model. We build the power library for each of those components and use them for the architectural-level exploration in low-voltage IoT application that support DVFS, mode transition overhead, and full IoT scenario. We show the power/energy analysis of asymmetric core architecture in an IoT scenario and the trade-off between energy saving and transition overhead in different sleep modes. | en_US |
dc.language.iso | zh_TW | en_US |
dc.subject | 物聯網 | zh_TW |
dc.subject | 功率評估平台 | zh_TW |
dc.subject | IoT | en_US |
dc.subject | Power evaluation platform | en_US |
dc.subject | Energy efficient | en_US |
dc.title | 用於低電壓物聯網架構之功率評估平台並以節能設計為例 | zh_TW |
dc.title | Power Evaluation Platform for Low Voltage IoT Architecture and Its Usage in Energy-Efficient Design | en_US |
dc.type | Thesis | en_US |
dc.contributor.department | 資訊科學與工程研究所 | zh_TW |
顯示於類別: | 畢業論文 |