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dc.contributor.author林妤珊zh_TW
dc.contributor.author林鴻志zh_TW
dc.contributor.author黃調元zh_TW
dc.contributor.authorLin, Horng-Chihen_US
dc.contributor.authorHuang, Tiao-Yuanen_US
dc.date.accessioned2018-01-24T07:37:56Z-
dc.date.available2018-01-24T07:37:56Z-
dc.date.issued2016en_US
dc.identifier.urihttp://etd.lib.nctu.edu.tw/cdrfb3/record/nctu/#GT070350132en_US
dc.identifier.urihttp://hdl.handle.net/11536/139352-
dc.description.abstract在本篇論文中,我們利用兩種不同的通道材料來製作薄膜電晶體,分別為氧化鋅(ZnO)以及氮化鈦(TiN)。為了要降低電阻電容延遲(RC delay)效應的問題,我們提出一種自我對準(self-aligned)的製程方式來製作上閘極(top-gate)氧化鋅元件。當元件線寬持續微縮時,我們發現寄生串聯電阻的影響會增加,並造成電流(on-current)和遷移率(mobility)的降低。可能是由於TMAH溶液在濕蝕刻時會滲透進去,因此會造成高達180kΩ的寄生串聯電阻,使得量測到的遷移率只有0.42 cm2/V-s,嚴重低於本質遷移率(intrinsic mobility) 9.49 cm2/V-s。因此,在未來的工作當中,要改善元件特性必須要先降低寄生串聯電阻。 氮化鈦為半金屬(semimetal)材料,此種材料至今仍尚未被應用於作為元件的通道。此篇論文當中,我們發現將氮化鈦材料之薄膜厚度從10奈米降低為1.8奈米時,電阻率會提高50倍,而當我們將閘極電壓從3V提升到5V時,載子濃度(carrier concentration)將會提高為1.02倍,而電阻率也會從57014 Ω-µm降低為55870 Ω-µm。雖然造成此種特性的原因不能排除是來自於量子侷限效應(quantum confinement effect),但在氮化鈦薄膜中氧含量的增加對其影響可能更為嚴重,因此造成通道厚度為七奈米的元件失去開關特性。 利用不同電阻率的氮化鈦來製作元件之通道層,可能是由於通道層載子濃度的差異,發現通道為較高電阻率的元件,特性上相較於低電阻率元件對閘偏壓有較大的變化。除此之外,利用多閘極(multiple-gated)的結構來製作此種半金屬材料通道層之薄膜電晶體時,開關比可以超過10,次臨界擺幅(subthreshold swing)也大約有2.6V/dec,都較優於上閘極結構之元件。zh_TW
dc.description.abstractIn this thesis, we fabricated and investigated thin film transistors (TFTs) with two kinds of materials, ZnO and TiN, as the channel layer. To decrease RC delay, we propose a self-aligned process to fabricate top-gate ZnO devices. As the channel length becomes shorter, we find that the RSD more significantly degrades the on-current and field-effect mobility. RSD of 180 kΩ is obtained. The cause for the high RSD is likely due to the permeation of the TMAH solvent during the wet etching process. Moreover, the measured intrinsic mobility of device is 9.49 cm2/V-s, significantly higher than the measured value of 0.42 cm2/V-s. Therefore, it is essential to advancing the device performance by dramatically reducing RSD in the future work. TiN is a material of semimetals which haven’t been used successfully as the channel layer of the devices. We find that the resistivity increases by 50 times as the film thickness of TiN is thinned down from 10 to 1.8 nm. We also show, by assuming that the effective mobility is a constant, as VG increases from 3V to 6V, carrier concentration will increase by 1.02-times, and the resistivity decreases from 57014 Ω-µm to 55870 Ω-µm. The above result reflects the action of field effect. Although the quantum confinement could be the reason for the ultra-thin TiN channels to exhibit such properties, the increased oxygen incorporation in the TiN film may be even more important in affecting the film properties. Moreover, the excessive oxygen incorporation makes the device with 0.7nm-thick TiN channel shows no tune-on behavior. By modifying the resistivity of channel layer, the devices with a channel of higher resistivity shows a larger variation ratio with increasing gate bias. Furthermore, by adopting a multiple-gated structure, the fabricated device exhibits an ON/OFF current ratio larger than 10 and subthreshold swing (S.S.) of 2.6V/decade.en_US
dc.language.isoen_USen_US
dc.subject金屬氧化物zh_TW
dc.subject氮化鈦zh_TW
dc.subject氧化鋅zh_TW
dc.subject薄膜電晶體zh_TW
dc.subject上閘極zh_TW
dc.subjectmetal-oxideen_US
dc.subjectTiNen_US
dc.subjectZnOen_US
dc.subjectTFTen_US
dc.subjecttop-gateen_US
dc.title氧化鋅上閘極薄膜電晶體及氮化鈦通道電晶體製作與特性分析zh_TW
dc.titleA study on the Fabrication and Characterization of Top-Gate ZnO TFTs and TiN-Channel TFTsen_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
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