氧化鉿閘極氧化層微縮在矽、砷化銦及砷化鎵銦金氧半電容之應用

Abstract

本論文研究不同高介電常數薄膜在矽、砷化銦和砷化鎵銦的應用。當閘極氧化層微縮，較高介電常數的二氧化鉿取代二氧化矽，相同電容值下擁有較厚的物理厚度，但其熱穩定性較三氧化二鋁差，漏電流也較大。本研究透過不同含量的鋁元素添加至二氧化鉿，來提高熱穩定性，同時維持較薄的等效氧化層厚度，及較低的漏電流。比較於堆疊三氧化二鋁和二氧化鉿，在矽基板上，以二氧化鉿薄膜添加鋁含量為2.57 % ( HfAlO )作為閘極氧化層，具有較佳的電特性。 此外，三五族材料擁有極高的電子載子遷移率，近年來更被廣泛的研究，期望能應用在小於10奈米製程的邏輯電路技術。為了成功的使用三五族材料，如砷化鎵銦、砷化銦等，取代原先以矽作為金氧半電晶體的通道材料，特別針對三五族材料的載子傳輸機制和介面特性做更深入的探討。但使用三五族材料作為電晶體通道材料，仍須克服幾個問題：高介電材料和三五族基板的介面缺陷密度Dit極高，需透過清洗方式的調整和前置處理( pretreatment )來有效降低Dit，以及在較薄的等效氧化層厚度下，同時擁有極低的漏電流。本研究以砷化銦和砷化鎵銦金氧半電容為主，並針對其介面做深入的探討。 文中探討三五族在沉積高介電材料之前，以不同的清洗前置處理方式對砷化銦基板的影響，此外，更透過沉積不同高介電材料來達到較薄的等效氧化層厚度，並以其介面缺陷密度的改善程度及低漏電流結果來驗證研究成果。使用稀鹽酸和氫氟酸清洗，以及TMA前置處理的砷化銦基板，有著較佳的電特性和物理特性。此外，在沉積HfAlO薄膜前，沉積一層較薄的三氧化二鋁可以維持較薄的等效氧化層厚度，同時具有較低的漏電流。 由本研究結果可知，鋁含量為2.57 %的HfAlO薄膜具有較好的熱穩定性，能夠符合不同基板對製程溫度的要求。在等效氧化層厚度減薄，HfAlO薄膜亦能提供較薄的等效氧化層厚度，同時具有較低的漏電流，因此HfAlO可為下一代閘極氧化層的選擇之一。

In this thesis, the different high-k dielectrics deposited on different substrates such as Si, InAs, and InGaAs. In order to realize high performance metal-oxide-semiconductor field-effect transistors ( MOSFETs ) devices, it is essential to have a suitable high-k gate dielectric with low interface trap density ( Dit ) , a low equivalent oxide thickness ( EOT ) and low leakage current. In the past, HfO2 which has a higher dielectric constant has been regarded as a replacement of SiO2 on gate dielectrics. Although HfO2 provides the thicker physical thickness as the same capacitance than SiO2, it has poor thermal stability and larger leakage current than Al2O3 which has a low dielectric constant. In this work, among the different high-k dielectrics deposited on Si substrates, we have found that the Al incorporated HfO2 film can be effectively improved it thermal stability and reduced the calculated equivalent thickness ( CET ) with low leakage current simultaneously. Compared with the HfO2/Al2O3 stacks, the HfAlO film with the Al concentration of 2.57 % demonstrated the CET about 2.08 nm and leakage current of 7.19×〖10〗^(-9) A/cm2 on Si. Moreover, III-V materials have been intensively studies for next generation logic devices beyond 10 nm nodes owing to their high electron mobility. In order to realize III-V materials as a feasible alternative channel for MOSFET in post-Si era, numerous of III-V materials, such as InGaAs, and InAs, have been studied to investigate its carrier transport and interface properties. To incorporate III-V materials as a channel in a MOSFET, high-quality dielectric/III-V gate stacks with low Dit, scalable EOT with low gate leakage current are mandatory. We investigated the characteristics of InAs-based and InGaAs-based MOSCAPs. Also, the same fabrications of high-k dielectrics on Si were transferred on InAs and InGaAs substrates to realize low CET III-V devices. The different chemical cleaning ways and pre-dosing of metallic precursors pretreatment for the III-V interface improvement were studied; besides, the impacts of interface properties on InAs and InGaAs with different high-k dielectrics deposition for the EOT reduction with low leakage current have been demonstrated. Substrates with HCl and HF solutions chemical cleaning and TMA in situ self-cleaning presented the better interface properties. Finally, with inserting Al2O3 inter-layer, the Hf-based film of HfAlO provided the good interface quality with a lower CET of 2.3 nm on InAs and CET of 2.7 nm on InGaAs. As the results, the Hf-based film of HfAlO with the Al concentration of 2.57 % demonstrated the better thermal stability, and it is important to form a stable interface within the best thermal budget of transistors fabrication process. It also provides the low EOT with low leakage current. The HfAlO film can be regarded as a promising gate dielectric of MOSCAPs for EOT scaling.