利用週期脈衝氧化結合臨場蝕刻技術改善表面特性之鍺通道鰭式場效電晶體

Abstract

鰭式場效電晶體的三維結構同時配合三重閘極結構，不僅有較大的等效通道寬度來導通電流，同時也擁有良好的閘極控制能力，能有效地抑制短通道效應；此外鍺材料的電子與電洞遷移率分別比矽大三倍與四倍，其製程與現今的矽製程技術相容，因此當元件隨著摩爾定律微縮至14奈米技術節點以下時，鍺通道鰭式場效電晶體被提出來提升元件特性。 然而鍺的表面容易產生不穩定的氧化物(GeOx)，這層氧化物會對元件產生不利的影響，因此本篇論文使用週期脈衝氧化技術在鍺通道表面成長一層0.4奈米的二氧化鍺(GeO2)當作界面層，能夠有效修復由電漿蝕刻所造成表面的傷害，同時減少界面缺陷密度與表面粗糙度來提升界面特性，搭配三氧化二鋁或二氧化鉿的高介電系數材料當閘極氧化層，藉此達到良好的電性。一般使用快速熱氧化技術來成長界面層不容易控制厚度，有較大的等效氧化層厚度，因此為了確保公平性，本篇論文在相同的氧化技術只比較不同通道寬度、閘極長度和通道高度對電性的影響；在不同的氧化技術之下，只比較界面缺陷密度與元件載子遷移率。 在N型鰭式場效電晶體可以得到很好的電性：67.8mV/dec的次臨界擺幅、1.7×105的開關電流比、7.8mV/V的汲極感應位障降低現象與2.6×1012eV-1cm-2的介面缺陷密度。利用週期脈衝氧化技術可以將平均介面缺陷密度降低至快速熱氧化技術的36.2%，並且提升81.4%的電子遷移率。在P型鰭式場效電晶體，平均介面缺陷密度降低至快速熱氧化技術的64.9%，同時提升32.7%的電洞遷移率。另外我們還發現相較於三氧化二鋁材料，二氧化鉿雖然有更高的介電係數，但是卻增加270%的平均介面缺陷密度與降低11.6%的電子遷移率，使整體電性表現不如預期。

Three dimensional FinFETs with tri-gate structure has wider effective channel width to conduct current and superior gate coupling to control channel, which can effectively suppress short channel effect. In addition, the electron and hole mobility of Ge are three and four times larger than Si. Moreover, Ge process is compatible with existing silicon process. Therefore, Ge FinFETs was proposed to improve electrical characteristics when the device scales down to beyond 14nm technology node by Moore’s Law. However, Ge is prone to grow unstable germanium oxide-GeOx on the surface, which has negative effect to the device. Therefore, we grow 0.4nm germanium dioxide-GeO2 on the channel as interfacial layer by using cyclic pulse oxidation, which can repair the plasma etching induced surface damage effectively. It also enhances the interface quality by reducing interface trap density and surface roughness. Combining with high dielectric materials such as Al2O3 or HfO2 for gate oxide, it can achieve excellent electrical characteristics. In general, growing interfacial layer by RTO technique is not easy to control the thickness, which will obstruct the EOT scaling of advanced technology node. In order to ensure the impartiality, we only discuss electrical characteristics in different condition of channel width, gate length and fin height in the same interfacial layer treatment and gate stack. In different gate stack, we only compare average interface trap density and carrier mobility, which is independent of EOT. We can obtain outstanding performance of n-type Ge FinFETs by using ozone cyclic pulse oxidation including S.S. of 67.8mV/dec, Ion/Ioff of 1.7×105, DIBL of 7.8mV/V and Dit of 2.6×1012eV-1cm-2. Cyclic pulse oxidation can reduce average interface trap density by 36.2% and increase electron mobility by 81.4% comparing with RTO technique. For p-type Ge FinFETs, it can also decrease average interface trap density by 64.9% and increase hole mobility by 32.7% comparing with RTO technique. Moreover, device with HfO2 dielectric material has 3.7 times higher of average interface trap density and 0.884 times lower of electron mobility compared to device with Al2O3 dielectric material. Though HfO2 has higher κ-value, it further degrades the overall electrical characteristics.