Full metadata record
DC FieldValueLanguage
dc.contributor.authorLee, Wan-Yuen_US
dc.contributor.authorJiang, Iris Hui-Ruen_US
dc.date.accessioned2014-12-08T15:19:35Z-
dc.date.available2014-12-08T15:19:35Z-
dc.date.issued2009en_US
dc.identifier.isbn978-1-60558-522-2en_US
dc.identifier.urihttp://hdl.handle.net/11536/13945-
dc.description.abstractThis paper proposes a new architecture of variability-tolerant chip-multiprocessor. To mitigate the impact of process variability on throughput and power, voltage and frequency islands are introduced into chip-multiprocessors. Thus, voltage island frequency island chip-multiprocessors enable per-core scaling on the supply voltage and operating frequency. It can naturally collaborate with dynamic voltage frequency scaling. The process variations are characterized through an analytical model, and are quantified through Monte Carlo analysis. Compared with the design without process variations, when 70 threads are run on a chip of 70 small cores, our results show throughput degradation is 0.06%, while power reduction is 36.27%.en_US
dc.language.isoen_USen_US
dc.subjectProcess Variationen_US
dc.subjectChip-Multiprocessoren_US
dc.subjectMonte Carlo Analysisen_US
dc.titleVIFI-CMP: Variability-Tolerant Chip-Multiprocessors for Throughput and Poweren_US
dc.typeArticleen_US
dc.identifier.journalGLSVLSI 2009: PROCEEDINGS OF THE 2009 GREAT LAKES SYMPOSIUM ON VLSIen_US
dc.citation.spage39en_US
dc.citation.epage44en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000293808200009-
Appears in Collections:Conferences Paper