針對可重組態單電子電晶體陣列具缺陷感知之合成技術

Abstract

隨著製程不斷地演進，功率消耗(power dissipation)對於電子電路與系統設計而言是一個重要的問題，而漏洩功率(leakage power)已逐漸成為功率消耗的主要來源。由於可重組態單電子電晶體陣列(reconfigurable single-electron transistor array)的超低功率消耗特性，已經被視為有希望延伸摩爾定律(Moore's Law)的元件之一。又因為奈米級的元件因為比較高的製程變化性通常都會有著比較高的缺陷發生率。然而，現存的大多數方法所提出的合成演算法都是假設目標單電子電晶體陣列上是沒有任何缺陷的，因此，使用這樣的方法在合成階段時預期映射出的結果可能沒有辦法正確的被映射到含有缺陷的單電子電晶體陣列上。本篇論文提出一個可以針對缺陷的種類以及位置來合成的演算法，此外，我們提出的方法可以從缺陷中獲得好處以至於可以更減少映射出來的面積。在某些情況下，在含有缺陷的單電子電晶體陣列中映射的面積甚至能比在沒有任何缺陷的單電子電晶體陣列中映射的面積還要小。實驗結果顯示，與現存的方法比較，我們所提出的方法能將陣列寬度進一步減少 11.7%。

As fabrication process exploits even deeper submicron technology, power consumption is becoming one of the most critical obstacles in most electronic circuit and system designs nowadays. Meanwhile, the leakage power is dominating the power consumption. Various emerging nanodevices have been developed to tackle the leakage power issue in recent years. The single-electron transistor (SET) is regarded as one of the most promising devices since several works have successfully demonstrated that it can operate with only few electrons at room temperature. Since nano-scale devices generally suffer from a higher defect rate due to high process variability, the reconfigurable SET array has been proposed for dealing with such issue. Nevertheless, most synthesis algorithms assume the target SET array is fault-free. Hence, the mapping result expected in synthesis stages may not mapped on a faulty SET array correctly. In this paper, we propose a synthesis algorithm that can aware of fault types and addresses. Furthermore, the proposed technique can take benefit from the faults to further reduce the mapping area. In some cases, the mapping area in a faulty SET array can be smaller than the area in fault-free array. The experimental results show that our approach can synthesis moderately large circuits in a reasonable runtime and reduce about 11.7% of width compared to the prior art.