閘極低介面缺陷的高介電係數堆疊以及鈀鍺合金對鍺元件之研究

Abstract

在這篇論文當中，首先我們發現當退火溫度從300℃ 上升至400℃ 時鈀鍺合金接面有明顯的蕭特基能障下降，這個蕭特基能障下降的現象在沉積較厚的鈀金屬上更為明顯(Pd ≥ 50nm)。鈀鍺合金接面在退火條件400℃下的漏電流劇烈增加至10^2 A/cm2，因此鈀鍺合金接面在退火條件400℃下有類似歐姆電性的行為，這個行為可以透過電腦軟體模擬很好的擬合，藉由假設電子蕭特基能障為0.57 eV，以及塊材缺陷密度為2E19 cm-3位於鍺能隙中間，我們利用缺陷輔助穿隧機制可以成功地解釋電性類似歐姆的行為。另外我們也進一步使用低溫量測確認接面缺陷電流和量測溫度的相依性，量測結果顯示缺陷輔助穿隧電流和量測溫度有很強的相依性，因此在室溫下鈀鍺合金接面在n型鍺基板上，在400℃ PDA這個條件下可以達到類似歐姆接面。 其次，我們使用微波氧化以及氧電漿氧化兩種方法成長~1奈米的二氧化鍺，並製作出二氧化鉿/三氧化二鋁/二氧化鍺/p型鍺基板之金氧半電容，探討兩種成長方式的二氧化鍺對電容特性的影響，其中微波氧化的電容在600℃,1min氮氣退火之下漏電流相較400~500℃大幅提升。從X光電子能譜分析上可以看到使用氧電漿成長的二氧化鍺氧化態比較接近理想的氧化態，表示使用氧電漿成長的~1奈米二氧化鍺比微波氧化成長方式有較好的介面品質。另外我們也比較不同高介電薄膜的堆疊，發現當二氧化鉿直接疊在二氧化鍺上有降低缺陷密度的趨勢，對二氧化鉿/三氧化二鋁/二氧化鉿/二氧化鍺/p型鍺基板之金氧半電容來說，可以得到低缺陷密度約5E11 eV-1cm-2，接著再經過一次後金屬退火可以使得缺陷密度下降到約3E11 eV-1cm-2。在材料分析上我們使用穿透式電子顯微鏡以及能量色散X射線光譜來觀察薄膜，可以看到在經過退火製程，鉿進入二氧化鍺中形成二氧化鍺鉿。 最後我們使用前面提到的高介電材料堆疊方式(二氧化鉿/三氧化二鋁/二氧化鉿/二氧化鍺/鍺基板)製作金氧半場效電晶體，p型元件的次臨界擺幅為136 mV/dec，電流開關比為5E4，在過驅動電壓為-0.75 V及汲極電壓為-1 V時，擁有驅動電流為11 μA/μm，n型元件的次臨界擺幅為219 mV/dec，電流開關比6E2，在過驅動電壓為0.53 V及汲極電壓為-1 V時，擁有驅動電流為2.16 μA/μm。另外使用全電導法萃取缺陷密度在鍺能隙中的分布，推斷缺陷密度最低處偏向價帶邊緣，並使用分電容法量測等效電洞遷移率，發現使用低缺陷的閘極堆疊方式(二氧化鉿/三氧化二鋁/二氧化鉿/二氧化鍺)所製作的元件遷移率比原本的堆疊方式高(二氧化鉿/三氧化二鋁/二氧化鍺)。

In this thesis, we found PdGe alloy junction on n-Ge had obvious electron Schottky barrier height decrement with annealing temperature raising from 300℃ to 400℃. The Schottky barrier height decrement of PdGe alloy junction on n-Ge was significant when the Pd deposition layer was thicker (Pd ≥ 50nm). The leakage current of PdGe junction on n-Ge with 400℃ PDA increased dramatically to 10^2 A/cm2. Therefore, the I-V characteristics of PdGe junction on n-Ge with 400℃ PDA showed “Ohmic-like” behavior. This behavior could be well fitted by TCAD simulation by assuming the electron Schottky barrier height was 0.57 eV along with bulk defect density was 2E19 cm-3 near mid-gap in Ge. The simulation results successfully explained the “Ohmic-like” behavior by “trap assisted tunneling” mechanism. Moreover, we further confirmed the temperature dependence of trap assisted tunneling current by low temperature measurement. The contribution of trap assisted tunneling current was strongly depended on the measurement temperature. Therefore, the I-V characteristics of PdGe junction on n-Ge at room temperature would get “Ohmic-like” behavior for 400℃ PDA. Next, we used microwave oxidation (MWO) and in-situ oxygen plasma oxidation (in-situ PO) to grow GeOx interfacial layer, and fabricated HfO2/Al2O3/GeO2/p-Ge MOSCAPs. In microwave oxidation process, the leakage current of MOSCAPs was increased significantly when the annealing temperature raised to 600℃. The XPS spectra showed that chemical oxidation state of Ge-oxide grown by oxygen plasma was closer to the ideal state (GeO2), which suggested that the ~1nm GeOx interfacial layer formed by in-situ PO had better quality than formed by MWO. Besides, we also investigated different combinations of high-k dielectric gate stacks. We found out that the trap density was reduced when HfO2 layer was deposited directly on GeOx. For the HfO2/Al2O3/HfO2/GeO2(in-situ PO)/p-Ge MOSCAPs, low Dit value of 5E11 eV-1cm-2 was obtained and could be further reduced to 3E11 eV-1cm-2 by post-metallization-annealing process. Physical characterizations such as TEM, and EDS were used to analyze the gate stack as well. During the thermal annealing process, Hf would diffuse and merge into GeOx matrix to form HfGeOx. Finally, we used the high-k gate stack mentioned above (HfO2/Al2O3/HfO2/GeO2) to fabricate MOSFETs. The S.S. of PFET was 136 mV/dec, and the Ion/Ioff ratio of drain current at VD= -1 V was around 5E4. Driving current of 11 μA/μm at VG-Vth=-0.75 V and VD=-1 V were obtained for PFET. The S.S. of NFET was 219 mV/dec, and the Ion/Ioff ratio of drain current at VD= 1 V was around 6E2. Driving current of 2.16 μA/μm at VG-Vth=0.53 V and VD=1 V were obtained for NFET. The distribution of Dit in band gap was extracted by full conductance method. The distribution trend suggested that the lowest Dit value might locate at the valence band edge. The effective hole mobility of HfO2/Al2O3/HfO2/GeO2 gate stack was higher than that of conventional HfO2/Al2O3/GeO2 gate stack.