無接面和反轉式環繞閘極多晶矽薄膜電晶體記憶體元件之比較研究

Abstract

近年來，隨著摩爾定律的發展，元件尺寸不斷微縮，閘極長度也日益縮減，當閘極無法有效控制通道時，伴隨而來的問題就是短通道效應，包括汲極引致能障降低、閘極引致汲極漏電流等負面效果，本實驗利用環繞式閘極結構包覆多晶矽奈米線通道，使得閘極更能有效控制通道，提高掌控能力，進而抑制短通道效應。 環繞式閘極多晶矽奈米線通道薄膜電晶體元件擁有良好的電晶體轉換特性，能在施加較低的汲極電壓1 V下，擁有較大的驅動電流 (~〖10〗^(-6) A)、低次臨界斜率 (170±20 mV/dec)和高開關電流比 (~〖10〗^8)，以及較低的汲極引致能障降低 (50±15 mV/V)。將元件應用在SONOS記憶體方面，則可利用環繞式閘極的角落效應提升記憶體特性，施加較低的寫入電壓13 V以及抹除電壓-16 V，可在短時間1 μs達到2 V左右的寫入臨限電壓變化量和1.5 V的抹除電壓變化量，擁有優秀的寫入與抹除效率；在元件可靠度上，也有良好的電荷儲存能力和元件耐久度，推算此元件在十年後仍可維持在2 V左右的電壓變化量，並且元件可反覆操作長到〖10〗^6以上。

Recently, the dimension of device and gate length scaling continuously along with Moore’s Law result to short channel effect (SCE) including drain-induced barrier lowering (DIBL) and gate-induced drain leakage (GIDL) since the gate couldn’t control the channel effectively. In this thesis, we use the poly-Si nanowire (NW) channel encased by gate-all-around (GAA) structure to enhance the gate controllability and suppress the SCE. In this research, the GAA poly-Si NW thin-film transistors(TFTs) device possess excellent transistor transfer characteristics including higher driving current ~〖10〗^(-6) A at low drain voltage 1 V , lower steep subthreshold swing (170±20 mV/dec) , high on/off current ratio ~〖10〗^8 and a virtual absence of DIBL (50±15 mV/V). It shows that the GAA SONOS memory device would improve the characteristics of memory due to the corner effect including excellent programming/erasing (P/E) efficiency that can achieve threshold voltage shift (ΔV_th) of 2 V at 13 V stress and ΔV_th of 1.5 V at -16 V stress in 1 μs. Moreover, the device also have better retention behavior expected to remain ΔV_th of 2 V after 2 years and great endurance characteristics that can program and erase up to 〖10〗^6 repeatedly .