完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | 江昀融 | zh_TW |
dc.contributor.author | 簡昭欣 | zh_TW |
dc.contributor.author | Chiang, Yun-Zong | en_US |
dc.contributor.author | Chien, Chao-Hsin | en_US |
dc.date.accessioned | 2018-01-24T07:38:11Z | - |
dc.date.available | 2018-01-24T07:38:11Z | - |
dc.date.issued | 2015 | en_US |
dc.identifier.uri | http://etd.lib.nctu.edu.tw/cdrfb3/record/nctu/#GT070250117 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/139618 | - |
dc.description.abstract | 在此篇論文中,首先我們在250度一分鐘退火下成功製造出鎳砷化銦鎵合金。該合金的片電阻(sheet resistance)只有傳統高參雜N型離子佈植砷化銦鎵三分之一倍。在250度一分鐘氮氣退火下的鎳砷化銦鎵合金/砷化銦鎵二極體開關電流比有四個數量極,該二極體之蕭特基能障(Schottky barrier height for electron)為0.18電子伏特。 其次,我們利用氧氣電漿來製造二氧化鉿/三氧化二鋁之n型砷化銦鎵電容。在分析了該電容之電容電壓特性以及X射線光電子能譜後,我們發現雖然電容的漏電被氧氣電漿大幅改善,但是卻嚴重破壞砷化銦鎵表面。若要達到更好的特性,必需在調整氧氣電漿的劑量。 最後,我們成功在磷化銦基板上製造鎳砷化銦鎵蕭特基n型金氧半場效電晶體。該電晶體的開關比為3.72×103,次臨界擺幅為115 mV/dec。我們更利用了等效電路模型來比較、討論電導法(conductance method)與全電導法(full-conductance method)之間的差異。而我們使用了全電導法所萃取出的表面缺陷密度(interface state density)約為1×1013 cm-2eV-1位於砷化銦鎵的價帶高0.52電子伏特的能階處。接著,我們使用電荷幫浦法(charge pumping method)萃取邊緣缺陷密度(border trap density),其邊緣缺陷密度落在1019到1020 cm-3eV-1 該缺陷密度之深度介於20到45埃。我們發現邊緣缺陷密度也會嚴重影響到元件電性的表現。 | zh_TW |
dc.description.abstract | In the beginning of thesis, we successfully fabricated nickel indium gallium arsenide alloy by post metal annealing (PMA) at 250 °C in N2 ambient. Moreover, the sheet resistance of Ni-InGaAs was lower than InGaAs heavily doped with n-type. The Schottky barrier height for electron was about 0.18 eV and the on/off ratio of Schottky junction was about 1.2×104. Secondly, HfO2/Al2O3/In0.53Ga0.47As nMOSCAPs were fabricated with O2 plasma treatment. We used C-V meter and XPS to analyze our MOCAPs. We found that although the leakage current of MOSCAPs were improved by the O2 plasma, the surface of In0.53Ga0.47As was damaged. Finally, we successfully manufactured InGaAs nMOSFETs on InP substrate with self-aligned nickel source/drain. The on/off ratio was about 3.72×103 and the sub-threshold swing was around 115 mV/dec. Furthermore, we used equivalent circuit model to discuss and compare the difference between the conductance method and full-conductance method. The Dit extracted by full-conductance method was about 1×1013 cm-2eV-1 at ET = EV + 0.52 eV. By charge pumping method, the border trap density was around 1019 to 1020 cm-3eV-1 and the depth of border traps was from 20 Å to 45 Å. Border traps had large impact on device performance. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | 砷化銦鎵 | zh_TW |
dc.subject | 金氧半場效電晶體 | zh_TW |
dc.subject | 二氧化鉿 | zh_TW |
dc.subject | 電導法 | zh_TW |
dc.subject | 全電導法 | zh_TW |
dc.subject | InGaAs | en_US |
dc.subject | MOSFET | en_US |
dc.subject | HfO2 | en_US |
dc.subject | Conductance Method | en_US |
dc.subject | Full-Conductance Method | en_US |
dc.title | 在砷化銦鎵金氧半場效電晶體上製造之高介電閘極氧化層堆疊結構的研究 | zh_TW |
dc.title | Investigation of HfO2/Al2O3/In0.53Ga0.47As Gate Stack Fabricated on In0.53Ga0.47As-channel nMOSFETs | en_US |
dc.type | Thesis | en_US |
dc.contributor.department | 電子工程學系 電子研究所 | zh_TW |
顯示於類別: | 畢業論文 |