高效能混合式多重路徑延遲迴授與多重路徑延遲交換架構和2^k基底串行交換之快速傅利葉轉換處理器設計

Abstract

近年，正交分頻多工 (Orthogonal Frequency Division Multiplexing； OFDM) 技術被廣泛的應用於各式通訊系統中，例如無線都會區域網路(Wireless Metropolitan Area Network: WMAN) 、無線區域網路 (Wireless Local Area Network； WLAN) 、無線個人區域網路 (Wireless Personal Area Network: WPAN) 及第四代行動通訊系統 (Long Term Evolution； LTE) 等等。在正交分頻多工系統中，快速傅立葉轉換 (Fast Fourier Transform； FFT)是其中不可或缺的主要運算之一，由於現代的通訊系統的資料傳輸率越來越高，使得快速傅立葉轉換處理器的吞吐量也必須提高，因此設計一個在高吞吐量下減少面積複雜度的快速傅立葉轉換處理器，為目前主要的設計議題，因此為了提高快速傅立葉轉換處理器的吞吐量，本論文使用管線化的快速傅立葉轉換處理器設計，並設計出下列兩個新穎的快速傅立葉轉換處理器設計: 藉由觀察，本論文發現，多重路徑延遲迴授架構與多重路徑延遲交換架構的優缺點可以互補，像是多重路徑延遲迴授架構擁有零調序記憶體的優點，而多重路徑延遲交換架構卻需要調序記憶體將輸入訊號做調序，或是多重路徑延遲交換架構使用到較少量的蝶型處理器，而多重路徑延遲迴授架構所使用到的蝶型處理器量是多重路徑延遲交換架構的兩倍，因此本論節這兩個架構提出一個混合多重路徑延遲迴授和多重路徑延遲交換的架構(mixed MDF and MDC FFT architecture; MDFC)，此架構可同時擁有多重路徑延遲迴授架構與多重路徑延遲交換架構的優點，另外本論文使用前饋式Radix-3的蝶型運算單元(Butterfly unit; BU)使此架構可用於處理多倍平行度2^k×3點FFT。 針對基底-2^k的快速傅利葉轉換演算法，擴充[8]所提出的連續交換之快速傅利葉轉換處理器，並觀察各個傳統基底-2^k的快速傅利葉轉換演算法，將連續交換之快速傅利葉轉換處理器做優化處理，提出基底-2^2的連續交換之快速傅利葉轉換處理器、基底-2^3的連續交換之快速傅利葉轉換處理器和基底-2^4的連續交換之快速傅利葉轉換處理器。

Recently, OFDM (Orthogonal Frequency Division Multiplexing) has been widely used in various communication systems, such as WMAN (Wireless Metropolitan Area Network), WLAN (Wireless Local Area Network), WPAN (Wireless Personal Area Network), and 4G mobile communication systems (Long Term Evolution ; LTE). In Orthogonal Frequency Division Multiplexing communication systems, Fast Fourier Transform (FFT) is an important computation in this system. Since the data transmission rate of communication systems is higher than ever, we need to promote throughput of fast fourier transform processor. It is an important issue that designing a FFT processor with low area complexity and high throughput. Since we want to design a high throughput FFT processor, we proposed two kinds of pipelined FFT architecture as below: It can be observed that pros of MDF and MDC architecture can make up each other’s cons. As such, we mix MDF and MDC architecture and propose a new architecture that has both advantages of fewer butterfly units like MDC FFT and free of input memory like MDF FFT. Additionally, we use the folded and reused FFT processor technique in [13] to optimize processor of MDF architecture. The feedforward radix-3 PE in [21] is adopted so that MDFC architecture can perform 2^r×3-point FFT. We also put a variable length unit in feedforward radix-3 PE so that the radix-3 PE can be used to perform 2^r-point FFT. We extend the serial commutator FFT architecture which is proposed in [8]. According to each conventional radix-2^k FFT algorithm, we optimized radix-2^k serial commutator FFT architectures. We proposed the radix-2^2 serial commutator FFT architecture, the radix-2^3 serial commutator FFT architecture and the radix-2^4 serial commutator FFT architecture in the thesis.