基於硬體計數器與感應器之處理器單元佈局估計

Abstract

由於現代製程技術的進步下，靜態耗電的影響日益嚴重，逐漸成為主要的耗電因素。且在進行靜態耗電的分析時需要處理器元件上的溫度分布，所以處理器的平面圖成為了我們不可或缺的資訊，但處理器之平面圖獲取不易，因此而阻礙了在靜態耗電分析上相關的研究。 本研究提出了方法可以從軟體的角度來去建構出處理器之平面圖，我們使用硬體上容易取得的資源像是：硬體計數器、硬體溫度感應器，用來作為我們的運算參數，同時運用特別設計的基準程式來調控硬體計數器與硬體溫度感測器，並且利用了元件發熱與熱在晶圓上之傳導關係作為我們處理器平面圖之演算法設計，以上述關係來推導出處理器之平面圖。

As the advance of technology, static power is not negligible anymore. Static power is becoming a significant part while talking about power saving issue, because static power occupies such a high percentage of total power. The variation of static power at runtime is intensifying since the operating temperature of microprocessor is elevating. If we would like to trace a detailed system-level thermal behavior and power simulation, the floorplan will be necessary. However, floorplan of a processor is usually confidential and may not be able to obtain. In state of the art technologies, there are two most common way to evaluate power and thermal. One is meter-based and another is counter-based. In this paper, we present a counter-based methodology to estimate floorplan of a target processor by running special design benchmark programs and referring associated counters/sensors data and combined public chip design parameter. We propose this counter-based methodology to estimate floorplan instead of using peripheral devices to achieve the goal. So we don’t need to specially re-process the integrated circuit (IC), our methodology is hardware-friendly. To validate our result, we can’t compare our floorplan to the real chip floorplan, because we have no idea how to get recent chip floorplans. It’s confidential to us, so we abort this method. Our solution is that we run numerous benchmarks in target chip and collect the thermal sensor data. We do the same thing in simulation with floorplan we generated, and compare the thermal sensor data. From that result, we can assume that we calculate a floorplan which has the similar thermal behavior with the real chip floorplan.