标题: 磊晶穿隧层穿隧电晶体之研究
A Study on Tunnel FET with Epitaxial Tunnel Layer Structure
作者: 王培宇
崔秉钺
Wang, Pei-Yu
Tsui, Bing-Yue
电子工程学系 电子研究所
关键字: 穿隧电晶体;能带间穿隧;次临界摆幅;Tunnel FET;Band to Band Tunneling;Subthreshold Swing
公开日期: 2015
摘要: 在本论文中,吾人针对利用能带间穿隧效应(band-to-band tunneling)作为操作机制的穿隧电晶体元件进行研究。为了瞭解此新颖元件的基本特性与设计考量,吾人针对源极端接面轮廓与缺陷辅助穿隧效应(trap-assisted tunneling)对于本体穿隧电晶体元件(bulk TFET)的影响进行探讨。为更进一步提升穿隧式电晶体元件的性能,吾人提出一种与互补式金属氧化物半导体(CMOS)制程相容的磊晶穿隧层(epitaxial tunnel layer)穿隧电晶体元件。同时藉由电脑辅助设计模拟软体(TCAD simulation)深入探讨互补式穿隧电晶体(CTFETs)的各项元件参数。吾人同时展示了使用互补式穿隧电晶体架构作为反相器(inverter)的特性,并与使用互补式全耗尽型绝缘层覆矽(Fully depleted siicon-on-insulator) 金属氧化物半导体电晶体(MOSFETs)反相器做比较。此外,吾人也同时实际制作互补式锗磊晶穿隧层穿隧电晶体并探讨其特性。
吾人首先针对源极端接面轮廓与缺陷辅助穿隧效应对于本体穿隧电晶体元件的影响进行探讨。藉由不同的源极端接面轮廓比较,吾人发现靠近闸极介面层的参杂浓度与轮廓对于穿隧电晶体有最大的影响。穿隧效率与穿隧方向同时也会受到源极端接面轮廓的影响。由于缺陷在空乏区对于元件的特性会有最大的影响,因此缺陷在靠近闸极介面与接面边缘会最劣化穿隧电晶体的特性。
了解穿隧电晶体基本特性与设计考量之后,吾人提出一种与互补式金属氧化物半导体制程相容的磊晶穿隧层穿隧电晶体元件来提升穿隧电晶体的特性。考量到制程整合与材料特性的因素,吾人采用锗-矽异质材料系统来验证磊晶穿隧层穿隧电晶体的概念。藉由结构工程与磊晶穿隧层能带工程,锗磊晶穿隧层P型穿隧电晶体可达到优异的元件性能。
为了达成互补式穿隧电晶体的结构,吾人针对锗磊晶穿隧N型穿隧电晶体进行研究。由于使用具有价带位移(valence band offset)的锗-矽异质材料系统,锗磊晶穿隧层N型穿隧电晶体可应用抑制低电场能带间穿隧的概念。吾人利用电脑辅助模拟软体来展示并探讨此抑制概念,同时可发现锗磊晶穿隧层电晶体的次临界摆幅(Subthreshold swing)特性可得到进一步提升。
吾人也对于互补式穿隧电晶体架构作为反相器的特性进行探讨并同时比较使用互补式全耗尽型绝缘层覆矽金属氧化物半导体电晶体架构作为反相器的性能。在操作电压小于0.4 V的时候,穿隧电晶体反相器具有较快的速度。然而由于较大的寄生电容效应,穿隧电晶体反相器有较高的功率耗损。根据功率-延迟的分析,穿隧电晶体反相器操作在0.2 V时可有较快的速度同时具有较低的功率损耗。
最后,吾人同时实际制作互补式锗磊晶穿隧层穿隧电晶体并对其进行探讨。锗磊晶穿隧层P型穿隧电晶体具有高穿隧电流、低漏电流以及良好的平均次临界摆幅特性(约100 mV / decade 持续到10 nA / μm)。吾人也针对闸极-源极电容进行研究并同时探讨其原因以及可能的影响。
In this dissertation, tunnel field-effect-transistor (TFET) utilizing band-to-band tunneling (BTBT) as the operation mechanism is studied. To realize the basic characteristics and the design issues for the novel device, the effects of the source junction profiles and the trap-assisted tunneling (TAT) on the bulk TFET are investigated. To further improve the TFET performance, a CMOS process compatible TFET with epitaxial tunnel layer (ETL) structure is proposed. Various device parameters of complementary ETL TFETs (CTFETs) are studied and discussed in detail by the TCAD simulation. The inverter characteristics based on the proposed CTFETs are also presented and compared with the inverter based on complementary fully depleted silicon-on-insulator MOSFET (CMOSFETs). Moreover, complementary Ge ETL TFETs are also fabricated and discussed.
The effects of source junction profiles and the TAT on the bulk TFET are firstly investigated. By comparing with different source junction profiles, it indicates that the doping concentrations and profiles near the gate dielectric interface have the largest influence on TFET characteristics. The tunneling efficiency and orientation are also affected by the source junction profiles. Because the defects located within the depletion region have the largest effect on the device characteristics, the defects located near the gate interface and the junction edge degrade the TFET characteristics the most.
After realizing the basic characteristics and design issues of TFET devices, a CMOS process compatible TFET with ETL structure is proposed to improve the TFET performance. Considering the process integration and material properties, Ge/Si hetero-material system is used to demonstrate the concept of the ETL TFET. Excellent device performance of Ge ETL pTFET is achieved by the structural engineering and the ETL band engineering.
To achieve the configuration of complementary TFETs, Ge ETL nTFET is investigated. Because the Ge/Si hetero-material system with the valence band offset is applied, the concept of the suppression of the low electric field BTBT (LE BTBT) can apply on the Ge ETL nTFET. The LE BTBT suppression concept is illustrated and discussed by the TCAD simulation. The S.S. characteristic of Ge ETL nTFET can be further improved.
The TFET-based inverter are also studied and compared with the MOSFET-based inverter. Better speed performance can be achieved as the VDD is below 0.4 V. However, high power consumption on the TFET-based inverter is observed due to the large parasitic capacitance of CTFETs. According to the power-delay analysis, TFET-based inverter exhibits not only better performance but also less power consumption as it is operated at 0.2 V.
Finally, complementary Ge ETL TFETs are fabricated and discussed. The fabricated Ge ETL pTFET exhibits high tunneling current, ultralow OFF-state current, and good average subthreshold swing (S.S. ~100 mV/decade up to 10 nA / μm). The gate-to-source (CGS) capacitance is also investigated. The origin and the possible influence of the CGS are also discussed.
URI: http://etd.lib.nctu.edu.tw/cdrfb3/record/nctu/#GT079811502
http://hdl.handle.net/11536/139829
显示于类别:Thesis