高介電材料金屬閘極塊材鰭式場效應電晶體製程參數分析與電特性建模之研究

Abstract

鰭式場效電晶體技術的導入是次22奈米技術世代半導體產業的一大進展。儘管16奈米高介電材料金屬閘極塊材鰭式場效電晶體正導入量產，製程最佳化的問題仍有改善之空間，例如：製程變異所導致的電晶體電特性的變動，以及新3D結構和新製程所引起的源極/汲極之串聯電阻萃取與建模的困難等。雖然文獻上，已有相關的研究，但是大都使用模擬來仿真製程和元件電特性的變異；已知有少數製程步驟被討論，但並未包括製程彼此間的相互影響效應，亦無相對應之製程解決方案。串聯電阻也沒辦法分開去萃取接觸層到鰭式場效電晶體的電阻、鰭式場效電晶體之磊晶外延成長的電阻、源極/汲極延伸電阻和閘極通道電阻，導致無法找出高電阻之製程問題。有別於目前已知方法論，若能由實際的製程與量測來系統化分析上述之議題，將有助於更穩健製程技術之研究。

本論文探討16奈米高介電材料金屬閘極塊材鰭式場效電晶體之製程變異對元件特性和振盪器操作的影響，製程變異參數含括前段至後段製程，同時考慮製程參數彼此間的相互影響，由此找出製程變異關鍵的源頭。進一步提出嶄新的電阻測試結構與解析模式用以釐清各區電阻，能夠量測從源極到汲極這整串的線性和非線性電阻的大小，研究所提的萃取模型，能成功分解各個部分的電阻，並能夠量測單根與多根鰭式場效電晶體電阻等，最後提出製程良率、性能與功耗改進方案。本論文架構如下。第二章討論塊材鰭式場效電晶體之重要設計規則篩選和驗證平台，能針對標準單元的性能做模擬，並同時對設計規則做最佳化。第三章討論16奈米高介電材料金屬閘極塊材鰭式場效電晶體之製程變異對元件和電路之敏感分析，應用資料探勘法找出製程間的相互影響以及製程變異關鍵的源頭。第四章討論提出新的電阻測試結構與解析模式用以釐清各區電阻，能夠量測單根與多根鰭式場效電晶體電阻，以及坐落於不同位置但是相同主動區的電阻。

首先，於第二章本研究提出新16奈米高介電材料金屬閘極塊材鰭式場效電晶體之設計規則驗證平台，能夠根據設計規則對晶片大小，良率和電路設計的影響性，快速且正確地篩選出重要設計規則。同時，此平台能將舊製程學習到的良率和性能風險經驗回饋到現在製程。研究發現只要用28%和53%的設計規則，就能分別含蓋50%和90%良率風險。另一方面，在早期設計規則發展的階段時，能夠在沒有晶片面積增加，良率損失下，以及考慮製程變異下，就能增加元件的性能，這對晶圓廠是很有好處的。研究上提出的性能模擬和最佳化平台，能針對標準單元的性能做模擬，並同時對設計規則做最佳化。性能模擬的方式是用RC萃取和SPICE模擬。最佳化是用幾何規劃法方式，在限定晶片面積下，將標準單元庫的性能提到最高。結果顯示，在改變接觸層重疊的設計規則後，NAND2的延遲有超過100%改善。若加大閘極到接觸層的距離，則良率可以50%提升。在技術開發初期，應用模擬來對設計規則和標準單元庫做最佳化以達到性能的提升；進入真正投片製造的過程中，會遭遇到各式各樣的製程問題。

尤其，當製造16奈米製程高介電材料金屬閘極塊材鰭式場效電晶體時，製程變異帶來的不確定性，將導致電晶體的良率和性能下降。本研究提出新的方法論來探討16奈米高介電材料金屬閘極塊材鰭式場效電晶體之製程變異參數對元件和振盪器的影響，同時找出製程變異的真正源頭並作電特性建模。由於有太多製程變異參數在先進製程中。所以，首先利用敏感度分析來篩選出重要的製程變異參數。然而，篩選出的製程變異參數，可能會受到不同製程之間彼此的相互影響。為了進一步能去解析出隱藏在製程之間的變異關係，研究首度提出，應用資料探勘來挖掘出真正造成元件和振盪器電性變異之製程變異的源頭。實驗結果顯示，雙層閘極隔離層，源極/汲極鄰近，和源極/汲極深度都對元件和振盪器的臨界電壓，飽和電流，漏電流，頻率，振盪器的靜態電流等電性變異有顯著影響。但應用資料探勘後，真正製程變異源頭是雙層閘極隔離層。在改變雙層閘極隔離層成單層閘極隔離層後，離子佈植的均勻度改善了。這使得元件的臨界電壓的電性變異有30%的下降。同樣的，振盪器的靜態電流的電性變異則有7倍下降的改善。

進一步，本研究討論如何提升16奈米高介電材料金屬閘極塊材鰭式場效電晶體之元件性能。而這當中的最關鍵瓶頸是源極到汲極這整串電阻的大小。這包括接觸層縱向和橫向的深度和寬度，接觸層到鰭式場效電晶體之界面的好壞，鰭式場效電晶體之磊晶外延成長的好壞，源極/汲極延伸的長度，以及閘極控制能力等。本研究提供嶄新的測試結構，能夠量測從源極到汲極這整串的線性和非線性電阻的大小。研究所提出的萃取模型，能夠分解各個部分的電阻，包含：接觸層到鰭式場效電晶體的電阻、鰭式場效電晶體之磊晶外延成長的電阻、源極/汲極延伸電阻和閘極通道電阻。這新的測試結構和萃取模型也能夠量測單根與多根鰭式場效電晶體電阻，以及坐落不同位置但是相同主動區的單根或多根鰭式場效電晶體電阻。若將此新的測試結構的源極到汲極的量測對調也可以偵測到製程不良所造成的電性不對稱問題。此新的測試結構和萃取模型能夠使得量測的和預測的線性和非線性串聯電阻有96%的吻合，並同時提供製程一個穩定的監測工具。

總之，本論文已研究16奈米高介電材料金屬閘極塊材鰭式場效電晶體之製程參數分析與特性建模。本研究提出的方法與結果，可提供晶圓廠參考，用以節省製程技術發展時間和研發成本，有效地獲得最佳設計規則和標準單元庫性能。再經由調整製程材料和製程技術，使得製程參數對元件和電路的變異影響能降至最低。同時也提供創新的測試結構和萃取模型，能夠分解各個部分的電阻，進而找出製程弱點，並加以改善，而達到整體製程變異改善和元件性能提升。

There is no doubt that FinFET is a milestone in the semiconductor industry for the sub-22-nm technological nodes. Even though 16-nm HKMG (high-metal gate) bulk FinFET has achieved massive production, process optimizations are still emergency to improve yield loss like devices’ characteristic fluctuations induced by inline process variations, high FinFET source/drain (S/D) linear and nonlinear series resistance owing to poor epi-growth, non-uniform distribution of current density in S/D, critical limitation of restrictive design rule, ultra-thin contact film, and complicated 3D FinFET structure, etc. There are relative studies discussing about above issues; however, most of them used simulations to generate process variation and device characteristic fluctuation or had silicon data but just focus on limited process steps; few of them paid attentions on process-dependencies; none of them proposed test structures to extract S/D series resistances resulting from S/D contact, S/D epi-growth fin, S/D extension, and the channel gate; there are also no test structures to monitor layout dependent effects of FinFET. Unlike other studies, if inline process parameters and measured data can be provided to systematically analyze above issues, it will be helpful for a robust process study.

This dissertation reports how fabrication in-line process of 16-nm HKMG bulk FinFET fluctuates device and circuit’s performance. The process covers from front-end-of-line to BEOL-end-of-line; it demonstrates how to extract hidden correlations among complex and a large number of in-line process parameters and how to trace the source of variations of in-line process parameters. Furthermore, this dissertation reports a novel test structure to measure linear and non-linear S/D series resistances. This technique enables us to evaluate each component of S/D series resistances resulting from the S/D contact, the S/D epi-growth fin, the S/D extension, and the channel gate. The S/D series resistance of fins on different layout locations of the same diffusion is characterized and modeled by connection with a specified S/D contact on it. A solution of the process optimization is then proposed to enhance yield, performance, and leakage. Chapter 2 states the design rule prioritization, verification, and optimization under process variation. Chapter 3 describes the process-dependence analysis for characteristic improvement of device and ring oscillator. Chapter 4 discusses the source/drain series resistance extraction and modeling.

New 3D structures of 16-nm FinFET’s devices result in new challenges for circuit designs, process materials, and process schemes. Circuit design is based on design rule (DR) which is an important interface between design and manufacturing. Design rule becomes more complex as the process advances to 16-nm and beyond. We first present a novel platform, so called systematic and statistical design rule verification (SSDRV), to fast and accurately prioritize key design rules which significantly impact the cost (chip size), the yield, and the circuit design. SSDRV provides a feedback mechanism to learn design risk from the previous generation. SSDRV shows only 28% and 53% 16-nm design rules can cover 50% and 90% top risks of yield loss respectively. On the other hand, early performance gains in the early design rule development without increasing the cost and the yield loss is a benefit for the foundry. We for the first time propose a novel platform to optimize DRs of 16-nm bulk FinFET by considering standard-cells’ performance, yield, area, and layout style, simultaneously. Standard-cells’ performance is evaluated by an innovative simulation via RC extraction and SPICE simulation. Mathematical geometric programming is utilized to optimize DRs to access the best performance of standard-cell with limited area. The result shows by optimizing the contact overlap, NAND2 has improved more than 100% delay without changing NAND2 area. Furthermore, by enlarging 2 nm spacing of the gate to contact, 50%-yield improvement could be achieved without increasing chip size. Even DRs and standard-cells’ designs can be optimized by simulation in the early stage of the technology, following production issues are really challenged and have to be overcome.

The most important concern of fabrication of 16-nm HKMG bulk FinFET is the process variation which causes yield and performance loss. We first report a novel method to discovery and optimize key fabrication in-line process parameters to improve performance and variability of devices and ring oscillators. The sensitivity analysis is first utilized to prioritize key in-line process parameters which significantly boost performance and reduce variations of devices and ring oscillators. After prioritizing key inline process parameters, there may be still many inline process parameters. Each inline process parameter may impact on each other. To extract hidden correlations among complex and a large number of in-line process parameters, data mining (DM) technique is applied to highlight and group associated in-line process parameters. The source of variations of in-line process parameters in each group is revealed by DM. By tuning process schemes or process materials of inline process parameters to reduce their sensitivity to fluctuate the characteristic of the device and Ring-Oscillator is proposed in the thesis. Results show the dual gate-spacer, the S/D proximity, the S/D depth, and the S/D implant are grouped into the same cluster and significantly affect threshold voltage, on-state current, off-state current, effective capacitance, effective resistance, frequency, and integrated circuit quiescent current (IDDQ). However, the variation source of these inline process parameters is the thickness of the dual gate-spacer. By replacing dual spacers with single spacers, the fluctuation of threshold voltage is 30% dropped. Furthermore, impacts of the on-state current ratio of N/P devices on RO frequency and IDDQ are also examined; by replacing dual spacers with single ones, the uniformity of implantation can be enhanced. Thus, the fluctuation of IDDQ is 7 times reduced and RO characteristic can fit to designing targets.

After reducing the process variability, we further discuss how to boost performance and improve yield for devices of 16-nm HKMG bulk FinFET. One key approach is to improve the S/D series resistance. However, an effective extraction of S/D series resistances is a challenging task owing to poor epi-growth and non-uniform distribution of current density in S/D, critical limitation of restrictive design rule, ultra-thin contact film, and complicated 3D FinFET structure. In this thesis, we for the first time report a novel test structure to measure linear and non-linear S/D series resistances. This technique enables us to evaluate each component of S/D series resistances resulting from the S/D contact, the S/D epi-growth fin, the S/D extension, and the channel gate, respectively. The S/D series resistance of a single fin or multi-fin can be characterized and modeled with the specified S/D contact on it. By the same way, fins located on the different layout but in the same active region can also be measured and extracted. Furthermore, the S/D series resistance of each fin can be analytically calculated by swapping the S/D bias condition. This swap test can detect the process issue of the S/D asymmetry. Finally, the proposed test structure and extraction technique shows the predicted S/D series resistance matches 96 percent of the measured S/D series resistance. It also provides a robust monitoring tool to diagnose a process weak point of the 16-nm HKMG bulk FinFET devices.

In summary, we have proposed an innovative approach for process-dependence analyses and electrical characteristic modeling of 16-nm HKMG bulk FinFET devices. This study has reported a novel method to optimize design rules and standard-cell design style considering standard-cells’ performance and size. We further presented an innovative methodology to optimize in-line process parameters by tuning process schemes or process materials to reduce their sensitivities to fluctuate characteristic of device and ring oscillator. A novel test structure and extraction was implemented to extract and model the source/drain series resistance.