標題: 可適應性調整間隔數目之間隔表面積啟發式包圍體階層建造單元
A Binned-SAH BVH Construction Unit with Adaptive Bin Numbers
作者: 王新憲
范倫達
Wang Hsin-Hsien
Van, Lan-Da
資訊科學與工程研究所
關鍵字: 階層包圍體;表面積啟發式;階層包圍體建造;光線追蹤硬體元件;bounding volume hierarchy (BVH);surface-area-heuristic (SAH);BVH construction;Ray tracing hardware unit
公開日期: 2016
摘要: 在本論文中,我們研究了在不同間隔數目下,建造間隔表面積啟發式包圍體階層所花費的時間,以及產生的加速結構對成像所需時間的影響,並提出針對連續場景以動態調整的方式決定每次建造包圍體階層所使用的間隔數目。在不需要事先知道場景資訊的條件下,於動態場景中與各種間隔數量的狀況比較所需時間,動態調整間隔的方式從花費的時間在任何場景中都能逼近最適合的間隔數量。同時,也設計了以動態調整的方式建造間隔表面積啟發式包圍體階層的硬體元件,並使用TSMC 90nm製程實現,模擬顯示,比起在Intel Core i5-4570 CPU上以visual studio 2013執行,此單元在125MHz時脈下執行建造程序所花費的時間平均僅需要0.095%的時間。
In this thesis, we examine the construction time of binned-SAH (surface area heuristic) BVH (bounding volume hierarchy) with different number of bins and the acceleration effect of those structures on rendering. Based on the result, we propose to adaptively adjust the number of bins to construct a binned-SAH BVH towards dynamic scenes. Compared the time consumption with different condition of bin number at dynamic scenes, the proposed construction method could approach the result of the most fit bin number in each scene. Furthermore, a binned-SAH BVH construction unit with adaptive bin numbers is implemented in TSMC 90nm CMOS process. The construction time through the proposed hardware unit operated at 125MHz needs only 0.095% times of the time worked on visual studio 2013 in Intel Core i5-4570 CPU.
URI: http://etd.lib.nctu.edu.tw/cdrfb3/record/nctu/#GT070256103
http://hdl.handle.net/11536/139859
顯示於類別:畢業論文