低電壓觸發矽控整流器在靜電放電防護上的設計與應用

Abstract

近年半導體製程的發展和製程微縮的發展趨勢下，達到了更低的功率消耗，更高的操作效率及更佳的積體電路整合能力，也微縮了閘極氧化層(Gate oxide, GOX)和通道長度，但元件微縮進入奈米製程後，卻意味著會導致其靜電防護能力的下降，也間接的造成電子產品可靠度上的不穩定性，此外薄閘極氧化層也擁有低崩潰電壓之特性，使得先進製程之靜電放電防護設計更具有挑戰性。 由於在先進製程中單位面積的製程成本非常昂貴，因此增加佈局面積意味著同時增加高額的晶片製造成本，這使得佔用大面積的靜電放電防護電路變得更加昂貴，因此如何設計出低佈局面積並同時具有良好的ESD耐受度之靜電放電防護元件，為本論文之主要研究主題。 在典型全晶片靜電放電防護設計架構之中能夠在靜電放電轟擊時，提供有效的電流放電路徑，但在先進製程之下對於典型全晶片靜電放電防護設計架構Negative to VDD mode (ND mode)和Positive to VSS mode (PS mode)是較薄弱的放電路徑，其靜電放電耐受能力主要由電源端與接地端的靜電放電箝制電路所決定，因此，在本論文的第二章提出了新架構的輸入輸出介面的靜電防護元件，利用PMOS/NMOS的結構和Dummy Gate的方式將傳統的矽控整流器(Silicon-Controlled Rectifier, SCR)加以改良，為了達到快速放電與改善低漏電的目的，利用閘極控制的方式使新設計的SCR元件擁有更低的觸發電壓(Trigger voltage, Vt1)，同時利用Dummy gate的方式避免了淺溝槽隔離(Shallow trench isolation, STI)結構在元件中放電路徑中形成阻礙，此外使新元件結構同時擁有寄生二極體和寄生矽控整流器的放電路徑，使其更有效的應用於全晶片靜電放電防護設計架構之中，並且同時改善了典型ND mode和典型PS mode必須透過電源端與接地端的靜電放電箝制電路的缺點。以上研究在 28 奈米的高介電係數/金屬閘極製程下實現。

除了於第二章提出的新型輸入輸出介面靜電防護元件，本論文第三章，將新型元件結構加以改良使其得以應用於電源端與接地端的靜電放電箝制電路，為了能有更好的靜電耐受度與更低的觸發電壓與更快的導通速度，也利用Silicide Blocking (SAB)的方式來提升元件均勻導通的能力與降低觸發電壓，達到元件最佳化的目的，並且搭配傳統靜電偵測電路，以利於達到低漏電，高ESD耐受度，快速導通速度的首要目的，其中也加入了傳統的矽控整流器(Silicon-Controlled Rectifier, SCR)元件和傳統基底觸發矽控整流器(Substrate-Trigger SCR, ST-SCR)進行一系列比較，其中除了優異的靜電耐受度包括人體靜電放電模型(Human-Body Model, HBM)及機器放電模型(Machine-Model, MM)、均勻導通、快速導通、大幅降低佈局面積之特性，同時也可免於栓鎖效應(Latch-up)的危險等優點，因此，此新型元件非常適合使用在製造成本高昂、閘極氧化層厚度越來越薄以及操作電壓越來越低的先進製程中作為靜電放電防護的元件，並於第四章提出未來可以將新元件應用於鰭式場效電晶體之結構。

With advanced CMOS technology, CMOS devices have been fabricated with thinner gate oxide, and the operation ability of integrated circuits can attain to high speed and low power consumption. However, with the scaling of CMOS technologies, the ESD robustness decreases and the reliability of production is unstable. In addition, ESD protection is more challenge to overcome because thinner gate oxide are equipped with the characteristic of low breakdown voltage. The layout area of advanced CMOS process would spend a huge cost. In other word, companies will spend a huge additional budget because the layout of ESD protection cells occupies large area. In this thesis, small layout area and decent ESD robustness are our targets to realize on our novel devices. A typical whole chip ESD protection scheme forms Positive to VDD mode (PD mode), Negative to VDD mode (ND mode), Positive to VSS mode (PS mode) and Negative to VSS mode (NS mod) which modes are discharge paths. However, ND mode and PS mode have relatively weak ability of ESD robustness, especially in advanced CMOS process. The ability of Power-rail ESD clamp circuits the main reason to influence ND and PS mode of ESD robustness. In chapter 2, we propose novel I/O ESD devices equipped with the advantage of low leakage and low trigger voltage. The I/O ESD devices are modified by Silicon-Controlled Rectifier (SCR). Meanwhile, we add the structure of PMOS/NMOS and dummy gate on our proposed I/O ESD devices. The advantage of gate-control method makes novel SCR devices have low trigger voltage (Vt1), while the benefit of attached dummy gate is Shallow Trench Isolation (STI) structure cannot form in our proposed devices. In addition, our proposed devices contain parasitic diode and parasitic SCR as discharge paths which can be usefully applied on whole chip ESD protection scheme. Moreover, the drawback of typical ND and PS mode are removed. From above all, our proposed design have been realized in 28-nm high-k/metal gate CMOS process. In chapter 3, we modify the novel devices described in chapter 2 and its modified devices can be applied on Power Rail ESD clamp circuit. Moreover, modified devices with additional Silicide Blocking (SAB) area to acquire better ESD robustness, smaller trigger voltage and faster turn-on speed. Modified devices combing with ESD transient detection circuit can efficiently turn on while ESD phenomenon occurs. We add traditional Silicon-Controlled Rectifier (SCR) and Substrate-Trigger SCR (ST-SCR) devices to compare with modified devices. Decent ESD robustness for HBM and MM, uniformly and fast trun-on, small layout area and the avert of latch-up risky are advantages for our modified devices in 28-nm CMOS process. In chapter 4, we predict that our proposed devices can be realized on Fin-FET structures for future investigation.