縮小化92-95 GHz 單晶片慢波分支耦合器

Abstract

本論文研討應用於92 到95 GHz 頻段之分支耦合器之縮小化，為了縮短耦合器中的四分之波長傳輸線長度本篇論文使用週期性的慢波結構，並在第二章先描述慢波結構之原理，並設計了四種型態的分支耦合器，分別利用折疊傳輸線以及周期性慢波結構在不影響特性的前提下縮小耦合器的面積，使其能順利地應用於單晶片系統。 第三章介紹國家奈米實驗室所提供之製程，利用此CMOS 相容製程才 得以實現本次製作的分支耦合器，所使用的製程步驟以及需要的儀器都會 在此處簡述。 最後第四章為實驗結果，實驗結果除比較不同型態之耦合器特性以及 縮小化程度，同時也會探討製程在不同條件下的特性，最後會檢驗製程在 晶圓中央與邊緣以及晶圓與晶圓間的變異性，以確保製程的可靠度，並提 供數據協助改善製程。

This thesis studies the miniaturization of the 92-95 GHz branch-line coupler.In order to shorten the length of the λ/4 transmission lines used in the branch-line coupler, we utilized the periodic slow-wave structure. In chapter 2, we will describe the theory of the slow-wave structure. We also designed four types of branch-line coupler for which folded transmission lines and periodic slow-wave structures are applied. The area occupied by the coupler can be reduced without performance degradation. Chapter 3 introduces the process provided by National Nano Device Laboratories. Branch-line couplers in this thesis are implemented in this CMOS compatible process. All steps and instruments involved in the run will be briefly introduced in this chapter. The measured results will be shown in chapter 4. In addition to the performances of the four types of couplers and area reduction, the performances in different conditions are discussed. In the end, wafer center-to-edge and waferto-wafer variations will be checked to ensure the reliability of this process. The measured data will help to improve the process.