應用於動態與可適應性電壓調變多核心處理器之抗PVT飄移數位低壓差線性穩壓器

Abstract

多核心處理器被廣泛用於手持式裝置、筆記型電腦與伺服器等應用，其中動態電壓調變與可適應性電壓調變等技術經常被用於降低處理器核心之電源功耗及提升處理器系統的散熱性能。此外，對每一核心獨立做動態與可適應性電壓調變可以使處理器的能量使用效率最大化。不過，當處理器中的核心增加時，使用片外切換式電壓轉換器來實現動態電壓與可適應性電壓調變等技術會顯得不符合成本並且無法達到快速且有效率的電壓調變。因此，全積體化的數位線性穩壓器被提出來並用於每一核心獨立的動態與可適應電壓調變。相比於其他類型的全積體化穩壓器，全積體化數位線性穩壓器可以達到快速且最有效率及最合乎成本的動態與可適應性電壓調變控制。然而，相比於類比線性穩壓器，數位線性穩壓器在穩態時會有電流量化誤差之現象，此現象會造成輸出端出現非期望的輸出電壓漣波。而此電流量化誤差會受製成、電壓與溫度之飄移的影響，進而影響輸出電壓漣波之大小。近年來，一些文獻致力於解決上述這些問題，這些文獻中所提出的技術雖然可以消除電流量化誤差而使輸出電壓漣波被消除，但是在輸出電壓漣波與負載調節上會存在著折中的設計，而這兩項因素都會使處理器性能降低。故本篇論文提出一用於多核心處理器且具有抗製成、電壓與溫度之飄移技術的數位線性穩壓器。所提出之技術可以使電流量化誤差在任何製成、電壓與溫度之飄移下最小化並且同時維持高負載調節之性能。

Multi-core processor have been widely used in battery-operated portable systems, desktop, and server applications, where dynamic voltage scaling (DVS) and adaptive voltage scaling (AVS) techniques are commonly employed to lower power consumption and improve thermal performance of the cores. To maximize the energy efficiency of a processor when using DVS and AVS, it is highly desirable to independently control the supply and the clock frequency for each core. As the number of cores grows, fast, cost-effective, and energy-efficient DVS and AVS schemes become prohibitively challenging to implement using off-chip switching regulators. Therefore, the fully integrated digital low-dropout regulators (DLDO) are used to achieve fast, cost-effective, and energy-efficient DVS and AVS schemes. However, the DLDO regulator has current quantization error (CQE) which produces an undesirable output voltage ripple. Moreover, the CQE of DLDO regulator is affected by process, voltage and temperature (PVT) variations, which represents the output voltage ripple of DLDO regulator depends on PVT variations. Recently, some techniques are proposed to remove CQE and thus reduce the output voltage ripple. Unfortunately, there always is a tradeoff between output voltage ripple and load regulation, which both degrade the performance of processor. As a result, the DLDO regulator with anti-PVT-variation technique is proposed in this thesis for resolve the aforementioned issues and this technique can minimize the CQE under any PVT variations and maintain good load regulation simultaneously.