利用低溫非晶態氧化銦鎵鋅技術之高壓電晶體與捲對捲製程

Abstract

最近幾年，因為非晶態氧化銦鎵鋅(a-IGZO)的優異性能，使得它吸引了很多研究者的注意，例如很高的場效遷移率，很低的次臨界電壓，以及大面積的均勻性。因為其高能隙值與低溫製程，IGZO材料的另一個有潛力應用是高壓操作元件。在邏輯電路中，隨著尺寸縮小，電壓也被持續的降低以達到更低的功耗。因此，一個可以連接低壓邏輯電路和高電壓輸入/輸出的功率模組將變得更加重要。另外，找到一個高密度堆積的解決方案以達到較低成本始終是一大挑戰。單石三維堆疊集成是一個充分利用第三維度的選擇。每個電路層直接製造在同一基板的電路層上面。上層元件的製程溫度要低，才不會損壞到下層元件。 首先，我們使用低溫原子層沉積(ALD)用於沉積氧化鋁做為閘極氧化層，在溫度低於攝氏120度下製造出非晶態的氧化銦鎵鋅薄膜電晶體。在正偏壓加速測試中元件的臨界電壓值表現出反轉現象，臨界電壓一開始往正方向移動，隨著時間會逐漸往負方向移動。這種非正常的不穩定度可以用兩個模型來解釋，包括電子捕捉和氫的釋放與遷移。 然後，我們提出了可在高電壓穩定操作的非晶態氧化銦鎵鋅薄膜電晶體技術，應用在單石三維堆疊集成相當有潛力，未來可實現單晶片整合之輸入/輸出功率模組。此技術使用低於攝氏200度的製程溫度，同時將正偏壓和負偏壓加速測試的不穩定性最小化。經由長時間可靠性研究，推測該元件可以在20伏偏壓操作 10年而沒發生介電質崩潰，同時維持可接受的導通電流值。 最後，我們使用上閘極自我對準結構，在無色PI基板上製作出高性能的非晶態氧化銦鎵鋅薄膜電晶體。其中所有薄膜都是在室溫下利用捲對捲多腔體濺鍍系統所沉積，適合未來低成本、大面積之軟性電子平台技術。

Recently, amorphous In-Ga-Zn-O (a-IGZO) has attracted much attention because of its superior properties, such as high field-effect mobility, low subthreshold swing, and large area uniformity. One of the promising applications of a-IGZO is the high-voltage transistor because of the high bandgap value and low-temperature fabrication process of a-IGZO. Since the supply voltage in scaled logic ICs is continuously reduced to lower power consumption,the power management circuits that can bridge the low-voltage ICs and high-voltage input/output have become increasingly important. Furthermore, it is always desirable to integrate high-density devicesat low cost. 3D monolithic integration is a viable option for employing the third dimension. Each circuit layer is fabricated directly on the previous circuit layers on the same substrate. However, the process temperature for the upper layers must be low enough to prevent damageson the lower layers. First, we investigate low-temperature atomic layer deposition (ALD) for depositing Al2O3 as a gate dielectric in amorphous InGaZnO thin-film transistors fabricated at temperatures below 120 oC. The device characteristics under positive bias stress exhibit a VTturnaround behavior from a positive ΔVT to a negative ΔVT. This abnormal positive bias instability is explained using a two-process model, including both electron trapping and hydrogen release and migration. Then, a reliable high-voltage amorphous InGaZnO thin-film transistor technology has been presented for potential applications of monolithic 3D integration on CMOS. By using a process temperature below 200 oC, the instabilities of positive and negative bias stress can be carefully minimized. The long-term reliability study projects that the device can be operated at 20 V for 10 years without catastrophic dielectric breakdown while maintaining acceptable on-current degradation. Finally, high-performance amorphous InGaZnO thin-film transistors are successfully fabricated on a colorless polyimide substrate by using a top-gate self-aligned structure. All thin films are deposited by roll-to-roll-compatible sputtering processes at room temperature. This a-IGZO TFT technology serves as a promising platform for future large-area, low-cost flexible electronics.