實現在 40奈米 CMOS之高密度腦神經訊號處理器

Abstract

在腦部功能研究中以及神經義肢實現上，具高整合及微小化之神經感測系統是近年來相當熱門的議題。本論文提出高通道腦神經訊號處理器應用在高密度神經感測系統當中，藉由取得數位的腦神經訊號之後分類且轉換腦神經訊號(EEG/ECoG)到不同頻段這種方式，擷取腦神經訊號之特徵；所提出的可配置式離散小波轉換是採用提升式離散小波轉換演算法，此演算法可降低計算電路複雜度，進而有效地降低整體面積和功率的損耗。此外，在這個設計中時間窗格跟母小波都可以根據應用不同而調整。為了應用在能量有限的微小化神經感測系統上，本論文也採用了一次性編成記憶體以及自動重置電路用來解決植入式無線傳輸系統的限制，像是需要規格較小的裝置以及使用的長壽度問題等。 藉由採用40奈米一般製程，本論文實現了一個一百二十八通道腦神經訊號處理器，可擷取一百二十八通道腦神經訊號之特徵，消耗了1.9211毫瓦功耗，面積為977547.61平方微米。此外，本論文更進一步將一百二十八通道腦神經訊號處理器利用2.5D異質整合技術將腦神經訊號擷取電路與無線傳輸晶片整合成高密度神經感測微系統上。

Highly integrated and miniaturized neural sensing microsystems are crucial for brain function investigation and neural prostheses realization for capturing accurate signals from an untethered subject in his natural habitat. In high-density neural sensing microsystems, a high-density neural signal processor is proposed for acquiring and classifying neural signal, and extracting the features of EEG/ECoG signals by filtering the neural signal into different frequency bands. Based on the lifting-based DWT algorithm, the area and power consumption can be reduced by decreasing the computation circuits. Additionally, both the time window and mother wavelets can be adjusted. Moreover, the integrated one-time programmable memory and self-reset circuit realized which meet some critical constraints for the implantable wireless neural sensing microsystems such as small factor form, ease of the longevity. The 128-channel neural signal processor are designed and implemented using TSMC 40nm CMOS general purpose with total area of 977547.61um^2 and power consumption of 1.9211mW. Moreover, this proposed 128-channel neural signal processor is also integrated in a high-density neural-sensing microsystem in 2.5D heterogeneous integration with wireless chip and neural signal acquisition chip.