穿隧式電晶體與金氧半場效電晶體異質結構之非同步可程式邏輯陣列設計

Abstract

穿隧式電晶體(The tunnel field-effect transistor, TFET) 被視為相當適用於低電壓電路設計的元件，藉由能帶間穿隧(band to band tunneling) 的特殊電流導通機制，可以突破傳統金氧半場效電晶體在低電壓區間次臨界擺福(subthreshold swing) 的極限。磊晶穿隧層穿隧電晶體(epitaxial tunnel layer TFET) 的新穎電晶體架構可與目前主流的金氧半場效電晶體製成相容，提供了穿隧電晶體與金氧半場效電晶體異質設計而達到低功耗電路的可能性，我們使用了異質混合的架構來達成非同步可程式化邏輯陣列的設計。使用穿隧電晶體與金氧半場效電晶體異質混合的邏輯設計，在邏輯區塊裡的非同步管線化階段邏輯設計(asynchronous pipeline stage logic)，可達到20% 到33% 的功 耗節省。而在開關與連接區塊，穿隧式電晶體組成的傳輸閘電路(transmission gate) 在4 種不同的組合下可獲得最大的功耗節省。由於穿隧式電晶體還在實驗室階段，故電晶體布局的資料還未完善，但是穿隧式電晶體與金氧半場效電晶體由於結構相似，電晶體布局也會相似，而在電路設計上電路的接點位置是一樣的。最後我們以暫行性的方法，先將非同步電路可程式邏輯陣列使用金氧半場效電晶體建構起來。當穿隧式電晶體的電晶布局正式取得之後，只要將最底層的原件稍做改變，即可實現使用金氧半場效電晶體與穿隧式電晶體混合的可程式化邏輯陣列。

The tunnel field-effect transistor (TFET) is a promising solution for low power circuit design. The unique BTBT conduction mechanism can break the S.S. limit in MOSFETs. ETL-TFET enables the heterogeneous integration of TFET and MOSFET in current CMOS technology to achieve energy savings. We use a heterogeneous structure to achieve a low-voltage asynchronous FPGA design. In the logic block, asynchronous pipeline stage logics provide an energy savings of 20%-33%. In the switch box and connection box, a TFET-based transmission gate achieves the lowest energy consumption of the various combinations. However, implementing heterogeneous circuits on chip requires overcoming challenges including the lack of a TFET layout. However, in circuit design, the layout is similar and the pin location in CMOS and TFET technology is the same. This work develop a methodology which temporarily uses TSMC 90nm MOSFET to demonstrate a asynchronous FPGA. Once a TFET layout becomes available, we will be able to implement the design with a heterogeneous structure.