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dc.contributor.author穆劍龍zh_TW
dc.contributor.author吳耀銓zh_TW
dc.contributor.authorMu, Chien-Lungen_US
dc.contributor.authorWu, Yew-Chungen_US
dc.date.accessioned2018-01-24T07:39:04Z-
dc.date.available2018-01-24T07:39:04Z-
dc.date.issued2017en_US
dc.identifier.urihttp://etd.lib.nctu.edu.tw/cdrfb3/record/nctu/#GT070261302en_US
dc.identifier.urihttp://hdl.handle.net/11536/140275-
dc.language.isozh_TWen_US
dc.subject失效分析zh_TW
dc.subject電性分析zh_TW
dc.subject漏電zh_TW
dc.subjectOBIRCHen_US
dc.subjectInGaAsen_US
dc.subjectThermal emmien_US
dc.subjectASICen_US
dc.subjectIPen_US
dc.subjectFourier Transformen_US
dc.titleVLSI漏電區域的定位與解析zh_TW
dc.titleThe Location and Root Cause of the VLSI Leakage Pathen_US
dc.typeThesisen_US
dc.contributor.department工學院半導體材料與製程設備學程zh_TW
Appears in Collections:Thesis