雙時序餘裕＋雙工作電壓：針對可變延遲設計的動態功耗降低

Abstract

Circuit performance has been the key design constraint for over a decade. Variable-latency design (VLD) paradigm was proposed for optimizing the overall performance in terms of throughput. In addition, process variations and aging effects manifest themselves as gate delay shifts, and in turn cause variability of circuit timing (timing variability). Required for dealing with the impact of timing variability better, detailed evaluation and analysis of circuit timing for VLD are actually not straightforward. In this paper, we present a systematic methodology for analyzing a VLD circuit, and identifying critical 1-cycle and 2-cycle paths/gates. After the criticality analysis, a VDD assignment framework based on genetic algorithm (GA) is proposed to minimize the power consumption of VLD. Our objective is making constructed VLD circuits more power-efficient and less vulnerable to timing variability. The proposed framework is experimentally verified to be runtime-efficient and able to provide promising results. On average, 21.73% power reduction is achieved with 8% timing margin, and only 4.6% area overhead is introduced.

Circuit performance has been the key design constraint for over a decade. Variable-latency design (VLD) paradigm was proposed for optimizing the overall performance in terms of throughput. In addition, process variations and aging effects manifest themselves as gate delay shifts, and in turn cause variability of circuit timing (timing variability). Required for dealing with the impact of timing variability better, detailed evaluation and analysis of circuit timing for VLD are actually not straightforward. In this paper, we present a systematic methodology for analyzing a VLD circuit, and identifying critical 1-cycle and 2-cycle paths/gates. After the criticality analysis, a VDD assignment framework based on genetic algorithm (GA) is proposed to minimize the power consumption of VLD. Our objective is making constructed VLD circuits more power-efficient and less vulnerable to timing variability. The proposed framework is experimentally verified to be runtime-efficient and able to provide promising results. On average, 21.73% power reduction is achieved with 8% timing margin, and only 4.6% area overhead is introduced.