數位控制以及降低輸出電壓鐮波與PI補償演算法的穩壓器

Abstract

數位控制穩壓器在暫態響應結束後常因為較高的操作頻率而在穩態產生電壓鎌波(LCO)。使用分佈式數位穩壓器（DLDO）的電壓調節已被確定為用於新多核處理器的有效電源管理的有效的技術。數位LDO（DLDO）可提供低電壓操作，更快的瞬態響應和更高的電流效率。但是更快的瞬態響應會導致巨大的過沖和大的輸出電壓鎌波。使他在穩壓的效果不理想。在所提出的設計中，輸出LV分級電路用於感測輸出電壓的位置，用於動態增益調變（DGS），PI補償和Clamping控制。透過在穩態下的Clamping控制，輸出電壓可以更穩定。 通過PI補償和DGS可以縮短瞬態時間。

Conventional digital low dropout (D-LDO) regulator usually suffers from the drawback of large output ripple during steady state after the transient response due to the limit cycle oscillation. On-chip voltage regulation using distributed Digital Low-Drop-Out (LDO) voltage regulators has been identified as a promising technique for efficient power management for emerging multi-core processors. Digital LDOs (DLDO) can offer low voltage operation, faster transient response, and higher current efficiency. But the faster transient response causes huge overshoot and big output voltage ripple. It is not a good power supply for regulator. In proposed design, Output LV Grading circuit is used for sensing the location of output voltage for dynamic scaling (DGS), PI compensation and Clamping control. Output voltage can be more stable by Clamping control in steady state. And transient time can be shorten by PI compensation and DGS.