4H型碳化矽溝槽式閘極金氧半場效功率電晶體之關鍵製程研究

Abstract

為跟隨節能減碳的全球浪潮，功率半導體界吹起了寬能隙材料(wide bandgap material)的旋風。相對於傳統矽基功率半導體，寬能隙半導體材料能夠大幅降低操作中的功率損耗，也因此被普遍認為將是新世代的功率半導體主流。寬能隙半導體材料不論在各方面特性表現都較矽來得更佳，然而其最大的缺點仍在於生產成本。本研究團隊的最終目標是發展出一套標準的4H型碳化矽之塹渠閘極功率金氧半電晶體(Trench gate power MOSFET)製程，並且要能達到極高的導通性能，與不凡的高電壓耐受能力。 在本篇論文當中，將介紹吾人針對塹渠閘極功率金氧半電晶體所開發的各種製程，包括碳化矽基板乾蝕刻、閘極氧化製程與局部氧化(LOCOS)製程。吾人開發出一套獨特的兩段式乾蝕刻技術，可以達到理想的U型塹渠結構，其擁有近乎垂直的側壁，與圓角化的底部角落。吾人也針對V型槽(V-grooved)結構另開發一套乾蝕刻技術，可以達到不同的傾斜角度，作為多樣化晶面的應用。 在閘極氧化的研究方面，本研究團隊率先提出4H型碳化矽在稀釋一氧化二氮環境下的氧化機制。針對應用氬氣稀釋一氧化二氮環境氧化製作的金氧半電容，其各項電性表現將會在本論文中作一全面探討。研究結果顯示，氬氣稀釋一氧化二氮氧化技術很適合應用於金氧半電晶體的標準閘極氧化層製作。 局部氧化技術在矽基半導體製程上已相當成熟甚至已被部份取代，然而在碳化矽製程上卻少有進展，其主要原因在於碳化矽的氧化速率限制。但吾人已證實，若經由一道預非晶化佈值(pre-amorphization implantation)，碳化矽的局部氧化是有可能達成的。在佈植離子種類上，吾人經由一系列的研究，選擇了一個最適合的離子。碳化矽的局部氧化製程甚至較矽製程中來得更簡易，但局部增厚的氧化層品質就成了另一關鍵。吾人測試了局部增厚氧化層的高溫可靠度，並探討其應用於元件絕緣時，相對於傳統化學沈積(CVD)氧化層，對活性區元件(如金氧半電容)可能造成的影響。 對於金氧半元件來說，在閘極中的二氧化矽與碳化矽的介面問題始終是個關鍵議題，因此吾人分析了二氧化矽與碳化矽不同晶面接觸之介面特性。塹渠閘極功率金氧半電晶體為一垂直式元件結構，其通道乃塹渠之側壁，因此吾人製作了塹渠式金氧半電晶體來專門分析側壁介面特性。側壁介面與在平面上之介面特性差異將會有一系列的深入探討。 在開發塹渠閘極功率金氧半電晶體的過程中，吾人面臨許多沒有想過的問題與挑戰，這些問題都會對製作出的元件特性有嚴重的負面影響。在本篇論文中，這些問題和挑戰都會被鉅細靡遺地記錄下來，並提出可能的解決之道。部份解法已經過驗證，這些經驗都將作為日後進一步研究開發的基石。

As the growing demand for power saving and carbon reduction, wide bandgap semiconductor materials are vastly discussed to be the next-generation power device. With a general reduction in power loss, devices made of wide bandgap semiconductor surpass Si power devices in almost every aspects except for production cost. The ultimate goal of our research is to develop a fabrication process of 4H-SiC trench gate power MOSFET that possesses high on-state performance and good high-voltage capability. In this dissertation, several processes in fabricating a 4H-SiC trench gate power MOSFET are developed, including SiC dry etching, oxidation, LOCOS technique. We developed a two-step dry etching process that can produce an ideal U-shape trench with a vertical sidewall and rounded bottom corner. We also developed another etching recipe for the V-grooved trench that can reach different crystal faces of 4H-SiC. Oxidation mechanism of 4H-SiC in dilute N2O ambient is first established by our research group. The electrical properties of the MOS capacitors using Ar-diluted N2O oxidation are studied. The results suggest that Ar-diluted N2O oxidation could be a standard oxidation technique for gate oxide formation in 4H-SiC MOSFET. LOCOS isolation, which has been a mature technique on Si, is still not developed in 4H-SiC process. The major barrier lies in the much lower oxidation rate on SiC. However, with a pre-amorphization implantation, we have verified that LOCOS process could also be applied on 4H-SiC. The ion species dependence is studied and discussed. The SiC LOCOS process is even simpler than the Si one, but some concerns about the LOCOS oxide quality needs to be examined. The high-temperature reliability of the SiC LOCOS oxide is investigated. The impact on the MOS capacitor device when changing conventional CVD oxide to LOCOS oxide is also discussed to verify the feasibility of SiC LOCOS. As the most critical limitation, The SiO2/SiC interface quality of the gate oxide on different crystal orientations is studied. Because the conduction channel of the trench gate MOSFET is on the trench sidewall, trench MOS capacitors are fabricated to investigate the sidewall gate oxide quality. The differences between the sidewall and the planar surfaces are studied and discussed. During the development in trench gate power MOSFET, we faced various problems and challenges that would have severe influences on the device performance and reliability. These issues are addressed, and some possible solutions are also provided and verified. Our experiences are deliberately recorded and would be the foundation for future researching works.