基於封包的正交分頻多工系統的效能分析與實現

Abstract

封包OFDM技術已被IEEE802.11的無線區域網路中所使用。眾所周知，同步的動作對接收機來說至關重要，這包括封包偵測(packet detection)、載波頻率偏移(carrier frequency offset, CFO) 估測、符元同步(symbol timing)、通道估計(channel estimation)等。為了解決這些問題，很多方法被提出，同時也進行了理論分析來評估其效能。本論文的目標有貳，在論文的第一部分，我們考慮了各個同步動作的效能分析，且經過推導，得出各種相關的錯誤率和均方誤差的表示式，我們的結果不是比已知的更準確就是前人沒有推導過的。在論文的第二部分，我們將封包 OFDM 系統，也就是 IEEE802.11a，作 FPGA 的實現，我們採用Mathworks 所提供的一模式化設計流程來設計收發器，而搭配AD9361射頻模組的Xilinx Zynq7000 FPGA平台則用於硬體的實現。模擬顯示，我們的分析可以正確地預測同步的效能，同時，實驗也證實我們的設計可以在真實的環境中運作。

Packet-based OFDM has been used in IEEE802.11 wireless local area networks. It is well known that synchronization operations are crucial for the receiver, including packet detection, carrier-frequency offset (CFO) estimation, symbol timing, and channel estimation. Many methods were proposed to solve the problems, and theoretical analysis was also conducted to evaluate the performance. The objective of this thesis is twofold. In the first part of this thesis, we consider performance analysis of the synchronization operations, and derive closed-form expressions for various error rates and mean-square-errors. It is shown that our results are either more accurate that the existing or not derived before. In the second part of the thesis, we consider the FPGA implementation of a packet-based OFDM system, i.e., IEEE802.11a. A model-based design flow provided by Mathworks is used to design the transceiver, while a Xilinx Zynq7000 FPGA platform with an AD9361 RF module is used for hardware implementation. Simulations show that our analysis can properly predict the performance of the synchronization operations. Also, experiments show that our design can function well in real-world environments.