下世代砷化銦鎵積體電路元件設計與特性模擬之研究

Abstract

我國過去數十年，半導體產業蓬勃發展。積體電路元件依循維持摩爾定律持續微縮，製程步驟的創新、立體通道元件結構的建立、以及高遷移率材料的使用，皆扮演著重要的角色。如今，技術節點已進入16奈米(或稱14或15奈米)世代，多閘極場效應電晶體元件與三五族半導體通道材料成為重要的研究方向之一；例如：砷化銦鎵多閘極場效應電晶體元件。然而，砷化銦鎵多閘極場效應電晶體元件的電腦模擬、設計與特性擾動分析的研究尚未被完整提出。 本研究使用與實驗校估過的量子修正傳輸模式元件模擬器，首先探討了砷化銦鎵三閘極場效應電晶體元件通道寬度及通道高度之變化對於電特性之影響。在同時考慮轉換和輸出電流特性、通道量子局限效應、短通道效應、以及製程可製造性的難易度下，根據有效通道寬度正規化後的電流密度分析得知，對於14奈米的砷化銦鎵三閘極場效應電晶體元件，當通道寬度為10奈米時，其較佳的通道高度可介於11到17奈米。進一步，研究上將具有不同銦、鎵成份的通道覆蓋層考慮於上述元件特性分析中，其中覆蓋層的導電帶低於通道層的導電帶。覆蓋層的厚度和成分比例影響元件的傳輸特性，若假設元件的導通/截止電流比大於1.7x10^6、次臨界擺幅小於72 mV/dec、以及汲極導致位障降低小於55 mV/V，研究得知具有4奈米厚的In0.68Ga0.32As通道覆蓋層元件具有最佳的特性。由於製程變異，通道形狀未必能維持理想的矩形(通道夾角為90度)，同時矽化鎳金屬閘隨機奈米晶粒亦導致特性擾動，研究上發現若矽化鎳晶粒平均大小在16奈米平方以下，通道夾角在85到90度間，臨界電壓與短通道參數擾動可控制在 7%以內。本研究探討的元件除了具有良好的直流特性，其282 GHz的截止頻率亦優於目前已知的研究結果。 本研究的第二部分探討14奈米全閘極奈米線場效應電晶體元件遭受氮化鈦金屬閘隨機功函數擾動的影響，並與塊材鰭式場效應電晶體元件做為對照比較。在相似的160 mV臨界電壓下，N型砷化銦鎵全閘極奈米線場效應電晶體元件導通/截止電流(2.37x10^-5/2.47x10^-9)的比值，比N型砷化銦鎵塊材鰭式場效應電晶體元件大3.5倍；雖然他們的次臨界擺幅相似，但是全閘極奈米線場效應電晶體元件空乏區電場強度受到汲極電壓調變的影響比塊材鰭式場效應電晶體元件來得低，因此全閘極奈米線場效應電晶體元件的汲極導致位障降低(37 mV/V)比塊材鰭式場效應電晶體元件小約30%。雖然砷化銦鎵有較高的電子遷移率，但是元件通道的結構主導了閘極電容值，因此由相同的有效通道寬度正規化後，砷化銦鎵全閘極奈米線場效應電晶體元件的導通電流(7.54x10^-4 A/µm)最大、矽全閘極奈米線場效應電晶體元件次之，矽塊材鰭式場效應電晶體元件的導通電流(3.53x10^-4 A/µm)最小。由於砷化銦鎵的能帶比矽低，因此砷化銦鎵元件的截止電流比矽元件大7倍以上。全閘極奈米線場效應電晶體元件遭受氮化鈦金屬閘隨機功函數擾動的影響，其臨界電壓擾動值比塊材鰭式場效應電晶體元件小，當氮化鈦晶粒縮小到3奈米平方大小時，不論是砷化銦鎵或者矽通道之全閘極奈米線場效應電晶體元件臨界電壓擾動值下降的趨勢最為明顯。不像平面場效應電晶體元件特性明顯受到隨機金屬功函數擾動一樣，由於更強的閘極到通道的控制力、薄通道厚度的載子量子化效應以量子電容效應，氮化鈦金屬閘隨機功函數的隨機位置效應對於全閘極奈米線以及塊材鰭式場效應電晶體元件臨界電壓擾動的影響與差異不大。砷化銦鎵元件在導通時其電子速度比矽元件快，且電子速度受到擾動的變化值比矽元件高15%，因此砷化銦鎵元件的導通電流標準差受到氮化鈦金屬閘隨機功函數明顯的影響。簡言之，砷化銦鎵元件因為材料能帶簡併效應的關係，會抑制氮化鈦金屬閘隨機功函數對於侷域表面電位的擾動，進而減低對於電子密度分佈的改變量，所以砷化銦鎵元件在線性區特性擾動的免疫力比矽元件好，同時受益於全閘極奈米線場效應電晶體元件對於通道的完全包覆，砷化銦鎵全閘極奈米線場效應電晶體元件導通電流受到的擾動比砷化銦鎵塊材鰭式場效應電晶體元件的來的小。 總而言之，本研究已致力於砷化銦鎵多閘極場效應電晶體元件的設計、模擬與分析，同時研究上亦建議適當的元件參數設定用以優化元件的特性。此研究成果可提供我國半導體工業界作為發展下世代三五積體電路元件技術的參考。

The semiconductor industry has developed fast for the past decades. To maintain the advancement of Moore’s law, innovations of fabrication process, device structures with vertical channel, and high-mobility materials play the significant roles on the complementary metal-oxide-semiconductor technology scaling. Nowadays, the technology node has extended to 16 nm, sometimes called 14 or 15 nm, and multiple-gate field effect transistors and III-V semiconductors are promising researches, such as InGaAs multiple-gate metal-oxide-semiconductor field effect transistor (MOSFET) device. However, the device simulation and analysis of characteristic fluctuation of optimal InGaAs multiple-gate MOSFETs have not been completely studied. In thesis, we firstly use an experimentally calibrated 3D quantum mechanically corrected device simulation to examine the electrical characteristics with respect to variations of channel fin width (Wfin) and fin height (Hfin) on InGaAs triple-gate MOSFETs. By considering the transfer and output curves, channel quantum confinements, short-channel effects (SCEs), and device manufacture ability, simultaneously, we find that the studied device with Wfin = 10 nm and Hfin varying between 11 and 17 nm has the satisfied characteristics. After that, a channel capping layer of In1−xGaxAs above In0.53Ga0.47As channel layer is further explored. Notably, the conduction band energy of capping layer varied with mole fraction is lower than that of channel layer. By considering the specification to be achieved, like on-/off-state current ratio (ION/IOFF) > 1.7 × 10^6 , subthreshold swing (SS) < 72 mV/dec, and drain-induced barrier lowering (DIBL) < 55 mV/V, we find that the aforementioned device with a 4-nm-thick In0.68Ga0.32As capping layer can provide optimal characteristics for InGaAs trigate MOSFETs. Owing to fabrication limits, rectangular channel may not always guarantee and NiSi-random-metal-grain-induced variability is getting considerable with device scaling. To suppress the fluctuation, the averaged grain size should be smaller than 16 nm^2 and the channel fin angle could be between 85◦ and 90◦, and the fluctuations of threshold voltage (Vth) and SCE parameters are less than 7%. Comparing with recent researches, we have achieved the larger ION/IOFF, the higher cut-off frequency of 282 GHz, and the lower characteristic fluctuations. Secondly, the impact of characteristic variation induced by TiN random work function fluctuation (WKF) on 14-nm gate-all-around nanowire (GAA NW) MOSFETs is examined, and GAA NW MOSFET is compared with bulk FinFET. Under the same Vth of 160 mV, the current ratio (2.37×10^-5/2.47×10^−9) of n-type InGaAs GAA NW MOSFET is 3.5 times higher than that of InGaAs bulk FinFET. They have the similar SS, but the DIBL is decreased by about 30% to 37 mV/V owing to the less influence of drain voltage modulation on electric field of depletion region for GAA NW MOSFET. Although InGaAs has the higher electron mobility, the structure of device channel dominates the gate capacitance. Hence, after normalizing by the effective channel width, InGaAs GAA NW MOSFET has the largest ION of 7.54×10^−4 A/µm, followed by silicon GAA NW MOSFET, and silicon bulk FinFET has the smallest ION of 3.53×10^−4 A/µm. Because the conduction band energy of InGaAs is lower than that of silicon, the IOFF of InGaAs devices are at least 7 times larger than that of silicon. The Vth’s fluctuation (σVth) of GAA NW MOSFET induced by WKF is smaller than that of bulk FinFET. As TiN grain size shrinks into 3 nm^2, the decrease trend of σVth is the most obvious for both silicon and InGaAs GAA NW MOSFETs. Unlike planar MOSFETs, the impacts of WKF random location effect on GAA NW MOSFET and bulk FinFET are insignificant due to the stronger gate to channel controllability, carrier quantization, and quantum capacitance effect. InGaAs device has the large standard deviation of ION (σION) owing to high electron velocity and 15%-high velocity variation. In brief, InGaAs devices possess the better immunity of fluctuation than that of silicon devices in the linear region because of the energy degeneracy effect of materials, where the electron density is less sensitive to the local change of surface potentials. Besides, the σION of GAA NW MOSFET is lower than that of bulk FinFET due to the nature of gate-all-around channel. In summary, this thesis has investigated the device design, simulation, and analysis of InGaAs multiple-gate MOSFET devices and has indicated the proper device settings for optimizing device characteristics. The results can be a useful reference for semiconductor industry as developing the integrated circuit device technology for the next generation.