標題: 應用單電感雙輸出交換電源轉換器達成動態電壓調整之高解析視訊數位類比轉換器
High Resolution Video Digital–to-Analog Converter with Dynamic Voltage Scaling through Single-Inductor-Dual-Output Switching Converter
作者: 周文昇
溫瓌岸
Chou, Wen-Shen
Wen, Kuei-Ann
電子工程學系 電子研究所
關鍵字: 數位類比轉換器;單電感雙輸出電源轉換器;動態電壓調整;交換式轉換器;能量轉換效率;Single-inductor dual-output;SIDO;Digital to analog converter;DAC;DC-DC converter;Dynamic voltage scaling
公開日期: 2014
摘要: 隨著行動裝置的蓬勃發展,伴隨高解析度視訊的需求與省電的綠能趨勢,本論文嘗試利用交換式轉換器來提供視訊數位類比轉換器電源的創新做法,來同時達到高能量轉換效率與高解析度的視訊數位類比轉換器。傳統高解析視訊數位類比轉換器往往需要二個穩定的直流電源或者透過直流穩壓器,才能達到好的線性度輸出,然而會有整體能量效率不佳的現象。本論文首次運用單電感雙輸出交換電源轉換器來同時產生薄閘氧化層與厚閘氧化層元件電源電壓,並運用動態電壓調整技術來達成高轉換能量效率。同時透過特殊的電路設計與布局技巧,是文獻上首次發表運用交換式電源且同時可達到本質十二位元的高解析視訊數位類比轉換器。 此論文首先回顧傳統視訊數位類比轉換器的設計原理,如元件的差異理論(Pelgrom Mismatch Model)與設計規格的需求。接著提出如何藉由創新的電路動態電壓調整設計(Dynamic Voltage Scaling, DVS)與布局技巧(Finger Split, Shift, and Separate, 3S)來減少元件差異同時達成高解析12位元的本質線性度規格。然後提出單電感雙輸出交換電源轉換器的電路架構,以及如何與DVS的設計整合來達成高能量效率的12位元視訊數位類比轉換器。針對交換式電源的雜訊(noise)與雙輸出電壓的交互影響(coupling),也提出了電路設計解決方案。後續以實際下線驗證的55nm互補式金氧半電晶體 (CMOS)製程的電路結果,與已發表文獻作品質因數(Figure-of-Merit, FoM)的比較。在考慮總能量效率下,此電路可提昇至少20%的品質因數(FoM),且是文獻上首次發表運用交換式電源且同時可達到本質(Intrinsic, without trimming) 12位元的高解析視訊數位類比轉換器。
This thesis proposes a 55 nm CMOS 12-bit current-steering video digital-to-analog converter (DAC) directly powered by the single-inductor dual-output (SIDO) switching DC-DC converter with the dynamic voltage scaling (DVS) technique to improve the efficiency. Dual-DVS control in both digital and analog circuits can effectively reduce power consumption. With various supply voltage, the video DAC can meet several different specifications in the power optimized (PO) mode. Furthermore, for DAC, the proposed 3S method, including separating, splitting, and shifting, achieves good DNL performance to 0.78/0.4 LSB (with/without SIDO converter) without additional calibration functions and suppresses the switching noise interference from the SIDO converter. Moreover, for SIDO converter, the cross-regulation performance is greatly improved in both transient and steady state to achieve lowest interference for the analog supply. The total power efficiency can be improved up to 11.5% and 28% in the DVS and the PO mode. The SIDO supplied DAC with the dual-DVS function achieves 69.88 dB spurious free dynamic range (SFDR) at the 1 V output swing. The proposed 12-bit DAC and SIDO module achieves compatible performance compare to the traditional method and has the benefit of area and energy efficiency.
URI: http://etd.lib.nctu.edu.tw/cdrfb3/record/nctu/#GT079211834
http://hdl.handle.net/11536/140706
Appears in Collections:Thesis