暫時性接合與雷射解膠技術於三維異質整合平台之研究

Abstract

本博士論文研究三維積體電路關鍵製程技術，內容包括新式暫時性晶圓級接合技術及混合接合製程，以應用於未來各種數位邏輯元件與不同基板間之晶圓級異質整合技術平台。此新式暫時性接合技術同時包含晶圓解離製程，而由過去研究成果顯示，晶圓解離製程可分為化學蝕刻解離、加熱解離(thermal slide-off)、雷射解離，綜合各別優缺點，此論文研究採用可室溫解離且高解離效率的雷射解離技術，且有別於過去所發展的暫時晶圓接合與雷射解膠技術。過去所使用的製程結構是在攜帶晶圓(玻璃晶圓)與具積體電路元件晶圓間再塗佈一層高分子材料，以此高分子材料進行晶圓接合與此製程後的雷射解膠技術，然而僅此一層高分子材料，在雷射解離過程中，所產生的熱以及未完全吸收的雷射能量會有損傷下層電路元件的隱憂，因此在此論文中探討的接合製程使用的是雙層接合結構，包含塗佈在玻璃晶圓上僅300 nm厚的解離層酮基高分子材料與塗佈在元件晶圓上的非感光型黏性層聚醯亞胺(HD-3007, DuPont Inc.)材料，而使用的雷射解膠機台為355 nm雷射源，此解離層酮基高分子材料相較於聚醯亞胺，具備對355 nm雷射的高吸收係數，即當進行雷射解膠時，解離層酮基高分子材料將吸收大部分的雷射能量(>90%)，這樣可確保不會有多餘的雷射能量損傷到下方的電路元件，解離後玻璃晶圓與元件晶圓可直接分離不須使用任何機械應力來達成分離，此最佳化接合結構於250 °C之機械強度經檢測，可承受後續具高溫、酸鹼環境等，且可將暫時接合後的元件矽晶圓背面減薄至100 μm並拋光以進行後續整合製程，元件經過接合製程與雷射解膠製程其前後的電性特性皆一樣並未損壞，具備標準製程之可靠度。接著進一步提出另一個替換的250 nm無機解離層非晶矽材料，以期可以縮短所需的解離時間，以降低製程機台成本並提高產出效率，透過測試可發現，非晶矽相較酮基高分子具更高的355 nm吸收係數，且在相同雷射解離條件下可達成較大範圍的解離面積，此成果可以讓原本解離一組4吋暫時接合晶圓所需時間減少至少1.5秒，即以單位時間1hr來算，每小時可增加至少35組的解離產能，同時此接合結構亦具備可靠的接合強度。 在異質整合堆疊各不同功能的元件晶圓間則需銅矽晶直通孔(Cu TSV)，然而在此矽晶直通孔後續所產生的熱應力是否會影響到上層的銅金屬連線，則是需要進一步探討的課題，本論文發現在所謂銅凸出(Cu pumping)效應下，後續環境在250 °C以下皆不會對其金屬佈線與電性特性造成影響。在完成銅矽晶直通孔製程後，將導入此晶圓級異質整合平台的另一階段:非對稱型混和式接合製程(asymmetric hybrid wafer bonding)，混合式接合技術可同時間形成高分子-高分子接合及金屬-金屬接合，可在低成本、單一製程中完成內金屬連線，同時外圍透過高分子材料保護內部電路，提供良好介電特性及防止內部金屬連線氧化的可靠度問題；我們採用高分子低介電常數(low-k) 正型光刻膠聚醯亞胺（PSPI）提供良好抗氧化與酸鹼環境保護及可靠的的接合強度，在低溫250 °C真空腔體內進行晶圓接合，並達成總接合厚度僅3 μm厚的混合式接合，透過此關鍵製程技術，即可實現不同功能性電路元件晶圓堆疊的異質整合技術平台。而相關電性與製程機制皆會在本論文中探討描述。 綜合上述，本論文提出並探討一個異質整合製程平台，透過最佳化暫時接合製程用以磨薄拋光矽晶圓背面，接續著製作矽晶直通孔與金屬連線，使用僅3 μm厚之非對稱型異質接合製程，將上下晶圓接合以達到晶圓級異質堆疊需求。

In this thesis, a new temporary bonding technology with an ultrafast laser-release process of less than 20 s for 4-inch wafer is presented, where a 300-nm-thick photolysis polymer and a layer of polyimide are served as release layer and adhesive layer respectively. The submicron thick photolysis polymer has a feature of high absorption of 355 nm laser in contrast to polyimide during de-bonding procedures. In addition, the thin temporary bonded structure contains high chemical resistance and the pull test values show great mechanical strength ability. Electrical characteristics of the CMOS devices before and after laser-release process are also investigated. The results show no degradation. Thus, this technology scheme has the potential to be used for temporary bonding and release in 3D integration applications. Moreover, in order to develop a high-throughput laser release technology, another reliable temporary bonding scheme with both inorganic amorphous silicon release layer and HD-3007 polyimide is proposed and investigated. The amorphous silicon has a larger ablated area than the photolysis polymer release layer owing to the high absorption coefficient of 355 nm laser. Combined with the promising auto-mechanically meander shape laser ablation path, larger ablated size in the amorphous silicon release layer leads to shorter laser release time and higher throughput effectively. The bonding scheme can be achieved within the optimized temperature of 210 °C under 1 MPa bonding force. In addition, chemical resistance, mechanical strength with reliability assessment, and thermal stability test are inspected on the bonded structure. There is no obvious degradation in the electrical characterization after laser ablation indicating that this temporary bonding scheme has high feasibility to be used for 3D integration and fan-out wafer level package applications. For the metal interconnect between stacking multi-functional thinned device wafer. It is important for Cu TSV to be reliable at the back-end-of-line (BEOL) procedure particularly during high temperature process step. Any unreliable Cu TSV may cause residual from thermal stress due to the mismatch of the coefficient of thermal expansion. Therefore, an investigation is conducted on the behavior of Cu pumping whether it will affect the electrical performance in BEOL integration. Two sets of Cu pumping with pitch sizes of 30 μm and 40 μm were annealed to measure their resistance at temperature lower than 250 oC. Based on the results, the narrow pitch of 30μm can be applied in processes with temperature below 250 oC for BEOL procedure in 3D integration. By utilizing asymmetric hybrid wafer bonding, TSV based device wafers can be reliably bonded and subsequently supplies significant amount of metallic interconnection with vertical integration. The bonding method combined with Cu/Sn solid liquid inter-diffusion (SLID) metallic bonding and PSPI polymer to oxide bonding system at bonding temperature of 250 oC is demonstrated. The total bonding layer thickness is about 3 μm, which supplies sustainable mechanical strength for permanent hybrid bonding. Besides that, the mechanical pull test and chemical resistance test to assess the bonding strength are investigated. The cross-sectional conformation utilizes scanning or tunneling electron microscope (SEM/TEM) is also discussed. Overall, a promising multi-functional heterogeneous integration platform combined with asymmetric low temperature hybrid wafer bonding and reliable high-throughput bi-layer temporary bonding with ultra-fast laser release technologies for 3D integration is provided in the future.