運用重新取樣技術實現具可程式化非均勻濾波器組之研究

Abstract

運用多率重新取樣的訊號處理技術來設計一個具有分數採樣率的線性相位濾波器組， 可以有效的降低次頻帶訊號處理的整體運算量。然而，當欲實作一個分數的取樣頻率轉換時，卻會大量加深硬體的運算複雜度。在本論文中，我們提出了一個直觀的排程演算法來解決實作分數取樣頻率轉換時所碰到的排程議題。我們實做出一個新穎的 10 毫秒，18 個次頻帶，1/3-octave quasi-ANSI 濾波器組架構。我們提出的 quasi-ANSI 濾波器組架構實踐在TSMC 90奈米CMOS高臨界電壓製成單元庫(cell library)並使用時脈閥(gated-clock)。 此硬體設計在處理24KHz的取樣頻率的語音下， 可在 480 KHz 時脈下操作， 只消耗約 79.9 μW。 此濾波器組比起目前所知的濾波器組設計， 就產生每個輸出所需的乘法量而言， 約可以節省 15% 的運算複雜度， 同時減少了 19.5% 的功耗， 並且更進一步的減少了 13.4% 次頻帶訊號處理的整體所需的運算量。此外，我們認為具有分數採樣率轉換在多率重新取樣的概念中，未來可能會應用到更多的系統上。為了找到這類架構間的共通性。藉由我們的觀察，原來的多相位的矩陣形式，可以被更進一步的用更精簡且更具規律性的晶格架構來實現。因此，基於晶格架構，我們提出了一個可以具可程式化的取樣頻率轉換器來實現可配置的架構。

By exploiting the multirate re-sampling signal processing technique to design a fractional rate linear-phase FIR filter bank, the overall complexity of the sub-band DSP algorithms followed by the filter bank can be efficiently reduced. However, the applied fractional sampling rate conversions (SRCs) complicates the hardware complexity of the filter bank when implementation. In this thesis, we proposed a straightforward scheduling algorithm for fractional SRC to address the above issue. Then, a new implementation of a 10-ms, 18-band, 1/3-octave quasi-ANSI filter bank is proposed. The proposed quasi-ANSI filter bank has also been implemented in TSMC 90 nm CMOS high-VT technology. The test chip can be operated at 480 KHz to real-time process 24 KHz audio and it consumes approximately 79.9 μW (@0.9V). Comparing that with previous state-of-the-art design, the proposed quasi-ANSI filter bank not only saves approximately 15% computation complexity, in terms of multiplications per sample, and approximately 19.5% power, but also reduces approximately 13.4% of overall complexity of the sub-band DSP algorithms followed by the filter bank. Besides, we think that the fractional sampling rate conversion in the re-sampling concept may be applied on more systems in the feature. For the purpose to find the commonality of these kind structure. By our inspection, the original polyphase matrix form can be further reconstructed with an elegant and regular lattice structure. Based on lattice structure, we have proposed a programmable sampling rate convertor to realize a configurable architecture.