互補型薄膜電晶體於積體電路與顯示器之應用課題探討

Abstract

近幾年來，半導體微縮進程面臨嚴峻的挑戰，奈米線及三維積體電路技術在突破摩爾定律(More than Moore’s Law)方面被寄予厚望，並吸引諸多機構投入開發，然而目前相關文獻以製程面的改進為大宗，鮮少探討其在電晶體層次(transistor level)之電路運作可行性。本論文分別就環繞式閘極無接面奈米線薄膜電晶體(GAA JL-NWTFTs)以及三維結構之複合式互補型薄膜電晶體(3-D hybrid c-TFTs)深入探討其在置入電路系統後，雜散電容的問題及基本邏輯電路的表現。在環繞式閘極無接面奈米線薄膜電晶體的部份，從佈局圖形及後模擬(post-simulation)結果，可以得知在元件製備時為了使奈米線被均勻性地懸吊，所採的方法衍生出額外的寄生電容，進而嚴重地影響元件在邏輯電路上的運作。而在三維結構之複合式互補型薄膜電晶體的部分，透過比較傳統二維平面結構與三維堆疊結構，以三維結構所構成的基本邏輯閘面積使用效率，整體來說，優於二維平面架構，但在邏輯電路運作上仍觀察到劣化的情形。此研究顯示，未來欲將環繞式閘極無接面奈米線薄膜電晶體及三維堆疊複合式互補型薄膜電晶體兩項技術商用化並應用於三維積體電路及系統整合型面板(system-on-panel)，如何在元件特性、佈局面積以及寄生效應等三方面取得平衡點是值得深究的課題。

Nowadays, nanowire and 3-D ICs technologies are highly emphasized by many organizations for possible solutions to the current limitations defined by Moore’s Law. Nevertheless, the explorations on their feasibility in transistor level circuitry haven’t been adequately surveyed. In this thesis, we investigate stray capacitance issue and electrical property in the application of circuitry for gate-all-around junctionless nanowire TFTTs (GAA JL-NWTFTs) and 3-D stacked hybrid complementary TFTs (hybrid c-TFTs) separately. For JL-NWTFTTs, according to layout diagram and post-simulation result, the process method to uniformly suspend the nanowire leads to additional parasitic capacitances, resulting in severe degradation of logic performance. For hybrid c-TFTs, comparing the conventional parallel and 3-D stacked structures in several basic logic cells, the area efficiency outperformed the parallel counterparts. However, the worsening logic performance is also explicitly observed. This study reveals the trade-off among device characteristics, area and parasitic issue, which should be considered for the usage of JL-NWTFTs and hybrid c-TFTs in the future 3-D IC and system-on-panel applications.