使用有機化學氣相沉積系統以介面差排陣列磊晶成長三五族銻化物材料對互補式金屬氧化物半導體之應用

Abstract

目前矽基互補式金屬氧化物半導體(Si-based CMOS)之電晶體尺寸已到很難再持續縮小的地步。在不久後的將來，三五族複合物半導體材料將可能成為製作超高速及低耗能電晶體的選項之一。其中，銻化銦鎵本身具有高載子遷移率，載子有效質量小、可調變之能隙等特性，將銻化銦鎵材料與砷化鎵或矽基板結合將有希望成為下一代金屬氧化物半導體。不過銻化銦鎵與砷化鎵由於存在極大晶格不匹配(large lattice mismatch>8%)、反相畴(anti-phase domains)及熱膨脹係數差異(thermal expansion coefficient mismatch)，使得在磊晶過程中需藉由差排(misfit dislocation)、螺紋狀差排(threading dislocation)及其他缺陷來釋放應力；特別是螺紋狀差排本身易延伸至元件通道層(channel layer)而造成非輻射複合(non-radiative recombination)並降低元件特性。因此，如何在極大晶格不匹配條件下成長高品質銻化銦鎵材料在砷化鎵或矽基板將是一大研究重點。 此博士論文主要聚焦在使用有機化學氣相沉積系統(metalorganic chemical vapor deposition system)並以介面差排成長模式(interfacial misfit dislocation growth mode)來成長高品質銻化銦鎵磊晶層於砷化鎵基板上。在極精密成長條件下，IMF陣列(IMF array)能被產生在磊晶層與基板間介面以快速釋放在磊晶過程中所產生高晶格應力能量(high lattice strain energy)以獲得低缺陷密度銻化銦鎵磊晶層。研究過程中發現磊晶溫度是IMF陣列是否產生與影響磊晶層品質之關鍵因素。銻化銦鎵中銦成分及銻化銦鎵磊晶品質也能藉由一層極薄的IMF銻化鎵緩衝層而獲得提升，當銻化銦鎵(銦成分<0.2)磊晶層之表面粗糙度小於1奈米及螺紋狀差排密度小於9.0 × 106 cm-2。 在此研究中高介電常數材料(氧化鋁(Al2O3))與銻化銦鎵磊晶層(In0.15Ga0.85Sb/GaSb/GaAs and In0.28Ga0.72Sb/AlSb/GaSb/GaAs)間關係亦被研究討論。研究結果顯示銻化銦鎵磊晶層與氧化鋁間價帶補償(valance band offset, VBO)與導帶補償(conduction band offset, CBO)皆大於2.9eV，這研究結果證明銻化銦鎵/氧化鋁結合皆適合應用在n-type及p-type金氧半場效電晶體，也為銻化銦鎵CMOS提供一個極為重要的指標。並且AlSb/In0.28Ga0.72Sb與AlSb/GaSb異質接合皆為type I (straddling gap)，其VBO與CBO皆大於0.4eV，表示此研究採用AlSb當作勢障層(potential barrier layer)足以抑制CMOS元件之電子與電洞反向漏電流。

As downsizing of Si complementary metal oxide semiconductor (CMOS) devices comes to a standstill, III-V compound semiconductor has been attracting extensively as a promising alternating material for realizing ultra-high speed and low power consumption transistors. Among III-V materials, the integration of InxGa1-xSb materials on GaAs or Si substrate has been considered as the next generation of CMOS devices due to its high carrier mobilities, very low effective mass, controllable band gap and band engineering as combining with other III-V materials. However, due to the large lattice mismatch (>8%), anti-phase domains, and thermal expansion coefficient mismatch, the material has to relieve strain energy through misfit dislocations, threading dislocations, and other defects. Specially, these threading dislocations often propagate vertically to channel regions of devices, contributing to non-radiative recombination and degrading device performance. Therefore, highly lattice-mismatched of InGaSb-based epitaxial layers grown on GaAs or Si substrates for CMOS application have attracted significantly attention. The majority issues of this dissertation focused on the growth of high quality InxGa1-xSb epitaxial layers on GaAs substrates under the interfacial misfit dislocation (IMF) growth mode by metalorganic chemical vapor deposition (MOCVD) method. By adjusting the growth conditions in a very narrow window, an IMF array is introduced and self-assembled at the epilayer/substrate interface to relieve the high lattice strain energy between the epilayer and substrate immediately. Thus, the epilayer can be achieved with very low defect density. It was found that the growth temperature is the main factor affecting the formation of the IMF array and the crystalline quality of the epilayer. The indium content and crystal quality of the InGaSb epilayer were enhanced by using a thin IMF GaSb buffer layer. In particular, the InxGa1-xSb (x < 0.3) epilayers showed very high quality with an rms roughness of <1.0 nm and the threading dislocation density of <9.0 × 106 cm-2. The band offset parameters of Al2O3 high-k dielectric and InGaSb epilayer via two heterostructures (In0.15Ga0.85Sb/GaSb/GaAs and In0.28Ga0.72Sb/AlSb/GaSb/GaAs) was investigated. The results showed that both valence band offset (VBO) and conduction band offset (CBO) value of the InxGa1-xSb (x < 0.3) epilayer and Al2O3 were larger than 2.9 eV. Thus, the integration of Al2O3/InxGa1-xSb (x < 0.3) is feasible for both n-type and p-type channel MOSFET application. These results are an important contribution for the trend of InGaSb-based single channel CMOS devices. Moreover, the type-I straddling gap of both AlSb/In0.28Ga0.72Sb and AlSb/GaSb heterojunction with the VBO as well CBO values higher than 0.4 eV indicated in this study makes AlSb material as a potential barrier layer to prevent both of electron and hole back leakage currents in MOS devices.