半導體先進製程的布林邏輯演算應用

Abstract

本篇論文提出一個改善井鄰近效應(WPE)的布林邏輯演算方法，亦是首次在半導體業界提出的，此方法是利用技術型電腦輔助設計(TCAD)對晶圓所計算出來的數據結果，定出一個Gate to TG的距離約0.5~0.6微米，這個值是井鄰近效應最小的臨界點值，再以臨界點值進行布林邏輯演算方法來改善元件的缺陷，同時也設計測試鍵(testkey)條件針對不同Gate to TG 的距離，不同的LOD與元件周圍的Dummy看井鄰近的效應。 布林邏輯演算是結合基本的布林操作與TLR (Topoligical layout rule)，經過光學鄰近修正（optical proximity correction，OPC）產生所需的光罩，如本研究，在元件上的電性看到的井鄰近效應 (WELL Proximity Effect)，經由布林邏輯演算Vt改善0.14mV而Idsat則是改善15.9% mA，最後在良率部份，其中在良率的BIN4是與井鄰近效應(WPE)強相關的，在與舊光罩比較之際也有大約2%~3%的改善，顯示新的邏輯演算方法與測試鍵(testkey)設計是有效改善元件的缺陷。 布林邏輯演算方法亦可應用在先進製程40奈米、28奈米、20奈米，甚至到14奈米，如dummy的填入、植入層光罩的製作，因此光學鄰近修正及布林邏輯演算在未來的製程的演進是重要的一環且緊密相連的，更是不可或缺的，也能有更新更廣泛的應用。

In this study, presented a method to improve WPE (Well Proximity Effect) by Boolean logical algorithm, and first time presented in semiconductor industry, this method utilized TCAD (Technology computer aided design) vs silicom computation date, formulated the spacing of Gate to TG around 0.5~0.6um, the value is the lowest of WPE, and progress Boolean logical algorithm to improved WPE defect, in the meantime, design testkey for spacing of Gate to TG individual, moreover, there is monitor WPE of LOD and around the device separate. Boolean algorithm is combined Boolean operation and TLR (Topoligical layout rule), through OPC (optical proximity correction) generated MASK, in device WAT of WPE, through Boolean algorithm, the Vt improved 0.14mV, and Idsat improved 15.9% mA, in the final yield BIN4 improved 2%~3%, which was strong correlation with WPE, and proof effective method of Boolean olgorithm. This boolean algorithm was applicable to the advanced technology such as MASK generation of implant layer and dummy fill in 40nm, 28nm, 20nm, even to 14nm, furthmore, optical proximity correction and Boolean logical algorithm is important on the evolution process in the future are closely linked, and also have more wider and novel application.