應用於神經訊號感測微系統之低功耗訊號感測轉換與記憶體電路設計

Abstract

本論文針對應用於高解析生醫感測之低功耗訊號擷取數位轉換以及儲存電路提供完整的分析與評估。一般而言，傳統的腦神經訊號擷取系統是藉由長導線與矽晶片進行連結，因而面積並非第一考量；然而在超高解析度腦神經訊號擷取微系統中，腦神經訊號感測轉換與儲存電路將與腦神經擷取電極進行整合，因此晶片電路之面積效益將隨之成為設計重點。此外，為避免過高的電熱量對腦皮質造成損害，低功耗更是不可忽略的考量；為進行更進一步的數位化分析，低功率小面積類比數位轉換器也將會一併進行介紹。同時，低功耗的隨機存取記憶體電路亦會是整個生醫訊號擷取系統的設計重點。因此，本論文將會以放大器、類比數位轉換器、以及隨機存取記憶體作為討論的核心。 微大腦皮質訊號藉由感測器收集電訊號後，首先需要一個低雜訊高輸入阻抗的神經訊號放大器。因此所設計之神經訊號放大器具有50~60dB左右之放大倍率，用以提供後級訊號處理及訊號分析，固定倍率設計同時亦有降低設計複雜度與面積需求的優點。在腦神經訊號擷取微系統中，感測電極和大腦組織介面中會產生直流偏壓，我們需要設計截止頻率在1赫茲左右的高通濾波器以避免放大器飽和問題；此外電路本身亦有低頻的閃爍雜訊，因此我們將採用電晶體式虛擬電阻以及截波穩定電路來設計高通濾波器與解決閃爍雜訊的議題 具面積效益之11位元低功率類比數位轉換器，利用了混合式延遲線輔助之循序漸進式架構。為了減少所使用之電容總量，提出的混合式類比數位轉換器是由3位元之粗調式延遲線類比數位轉換器以及8位元細調式的循序漸進式類比數位轉換器進行整合。其中延遲線類比數位轉換器是由一個電壓時間轉換器及時間數位轉換器所構成，利用此延遲式轉換器可將類比電壓轉換為熱代碼而後進一步轉換成3位元之數位碼。為紓緩在細調電路端之比較器精準度需求，我們將採用提升式搜尋演算法。一部分將電壓移至高於電晶體的截止電壓，也作為粗調及細調之間的連接橋樑；為了更進一步降低整體功耗，我們將採用雙電壓、電源閘控制技術。透過將部分存在粗調以及微調電路中的數位區塊進行降壓，而類比部分區塊則操作在高電壓的方式來達到省電以及維持訊號轉換準確度的效果；為更進一步減少漏電流，利用動態地調整各群組的操作電壓，在該區塊不需要動作時，關掉其電源使其進入浮接狀態，可以有效的避免不必要的能源消耗。 微大腦皮質訊號經由特徵轉換擷取後，亦需要低功耗儲存電路來暫存處理之數據。超低電壓隨機存取記憶體儲存單元，設計目標旨在提升隨機存取記憶體的穩定性和可靠性，周邊電路也針對讀寫衝突設計寫入幫助電路及讀出幫助電路。利用10電晶體式近/次臨界隨機存取記憶體存儲單元，相較傳統隨機存取記憶體，擁有具有三態輸出線路，可減少輸出線路之漏電與切換動態功耗，在超低操作電壓0.35伏特具有54%的功耗減免。此10電晶體式記憶體單元可操作在 0.35 伏特至 1.2 伏特。本論文亦提出以傳統6電晶體式隨機存取記憶體儲存單元組成之迷你陣列。相較於利用一般邏輯規則布局之多電晶體儲存單元，迷你陣列具有小面積以及超短輸出線路的特性。透過降低輸出線路的負載、漏電、雜訊耦合以及電荷注入所引起之干擾，來達到超低電壓操作之可能性。除此之外，利用迷你陣列架構更可以有效避免因不平衡長寬比所造成之製程良率下降。此6電晶體式迷你陣列記憶體單元可操作在0.5伏特至 1.2 伏特，讓使用可以更加有彈性。

Investigating and monitoring the human brain activity has attracted prominent attention for bio-medical applications. One of substantial challenges is to develop high-density microsystem for real-time recording. Low-Power signal acquisition and memory circuit are crucial in the devices for preventing the damage during monitoring. Furthermore, area-efficiency is also a concern for integrating and miniaturizing neural sensing microsystem. Therefore, area-power efficiency neural signal conversion and low-power memory circuit have been investigated for high-density neural sensing applications. Firstly, for neural acquisition, we present an energy-efficient low-noise 16-channel neural-signal acquisition IC. The 16-channel acquisition IC comprises 16 low-noise analog amplifier with pseudo-resistor and 4 area-power-efficient 11-bit hybrid analog-to-digital converters (ADC). In this design, differential difference amplifiers (DDAs) design is used for achieving low-noise and energy efficiency. Additionally, the modified pseudo resistor with symmetric resistance property is designed to remove high DC offset from input signal. Moreover, the 11-bit hybrid ADC is designed by combining a coarse-tuning 3-bit delay-line-based ADC and a fine-tuning 8-bit successive approximation register (SAR) ADC to reduce area and power consumption. And follow up the previous 16-CH design; an area-power-efficient 64-Channel (64-CH) acquisition IC is proposed for further enhancing spatiotemporal-resolution. This 64-CH acquisition circuitry is composed of 16 4-CH low-noise digitally-assisted chopper-stabilized DC-compensation neural amplifiers and 16 area-power-efficient hybrid ADCs. The proposed 4-CH neural amplifiers is designed by using four DDAs and one shared chopper-stabilized DC-compensation circuitry. Furthermore, a dual-voltage SAR ADC with a self-timed power-management unit (ST-PMU) is designed to reduce power consumption and mitigate leakage. Secondly, in order to store and process information, low-power sub/near threshold SRAM designs are also proposed, including the disturb-free symmetrical 10T subthreshold SRAM with tri-state bit-line and the mini-array based 6T SRAM with Vtrip-tracking write-assist. In 10T cell design, the disturb-free feature facilitates bit-interleaving architecture that can reduce multiple-bit errors in a single word and enhance soft error immunity. The fully-symmetrical cell structure provides balanced performance in advanced strained-silicon and/or FinFET technologies where PMOS strength approaches that of NMOS. The tri-state BL is left floating in standby state to minimize switching activity for energy efficiency. To maintain manufacturability, the array of mini-array based 6T cell SRAM is built on foundry 4-by-2 mini-array with split single-ended large signal sensing to enable ultra-short local bit-line (LBL) of 4 bit length to improve variation tolerance and performance, and to reduce disturb. Moreover, the cell Vtrip-tracking write-assist (VTWA) design lowers the column cell supply to cell inverter trip voltage (Vtrip) to enhance write-ability while providing PVT tracking capability to ensure adequate data retention margin for unselected cells in the selected column.