無接面與反轉式閘極全環繞複晶矽奈米線電晶體之特性比較與閘極偏壓可靠度分析

Abstract

無接面(junctionless, JL)電晶體具有製程簡單以及低熱預算的優點以外，同時有極佳的抗短通道效應。因此被認為極具有潛力作為取代傳統通道反轉式(inversion mode, IM) MOSFET金氧半電晶體於3D ICs 製程。在本研究當中，我們利用光罩上不同設計條件與製程參數來與傳統多晶矽電晶體做特性比較，另外再深入探討其閘極不同正偏壓下之可靠度測試。 首先，我們提出利用奈米線(Nanowire，NW)結構以及環繞式閘極(Gate-All-Around，GAA)大幅提升閘極對通道的控制能力以抑制漏電，並同時改善次臨界擺幅(subthreshold slope，S.S.)與短通道效應控制能力。在本研究中，我們成功製作出IM-GAA-NW與JL-GAA-NW 之poly-Si TFT在不同閘、汲極重疊程度、n+與p+閘極、不同通道長度、不同NW根數以及短通道之特性討論：(1) IM與JL在閘極-汲極重疊(Overlay，OL)及閘極-汲極對齊(Align，AL)此兩種設計，特性上並無太大差異。 (2) JL 之 p+閘極在臨界電壓(threshold voltage，Vth)、S.S、汲極引致能障下降(Drain Induced Barrier Lowering，DIBL)及開啟電流(Ion)的表現上皆遜於n+閘極。可能成因為n+閘極為in-situ摻雜，而p+閘極是由離子佈植進行摻雜，在未經足夠高溫活化的p+閘極導致較差的閘極對通道的控制能力。 (3) IM與JL在通道長度由400nm縮至250nm時，會有更小的Vth及S.S.，Ion則有較佳的表現。而JL在S.S.的表現較IM優異但Ion略小於IM。 (4) JL在NW的根數由2根奈米線增至20根奈米線時，Ion會隨著根數增加而提高，S.S.、Ioff與DIBL則無太大差異，因此可藉由多通道奈米線達到更高的Ion。 (5) JL在製程上透過兩次側壁硬式光罩(Spacer Hard Mask，SPHM)將通道長度由光罩上圖案的250nm大幅縮至60nm之階梯式短通道，進而使S.S.及Ion有更佳的表現。 再來我們使用傳統直流(DC)電性量測技術來有系統地研究關於閘極正偏壓不穩定性(Positive Gate Bias Stress Instability，PGBI or PBS)於常溫下之劣化機制，分別對IM-GAA-NW、JL-GAA-NW以及單閘極超薄體(Single Gate Ultra Thin Body，SG-UTB)電晶體元件通入不同閘極過載電壓(Gate Overdrive Voltage，VOD)由VOD=1V, 2V, 3V到4V。實驗結果顯示，不論是IM或JL元件，皆有一Vth shift 之轉折點於PBS條件為VOD=3V。IM元件在施加VOD=3V~4V 持續1000秒的PBS的條件下，汲極電流衰減率(Id Degradation Rate)與轉導衰減率(Gm Degradation Rate)皆較JL來的嚴重，我們將此歸因為：當施加相同的閘極過載電壓於IM和JL元件上，其閘極氧化層電場與通道電場因傳導機制不同而發生改變，導致IM 在Ion與Gm的衰減較JL明顯 ; 然而在VOD=1~2V的條件下，Ion Degradation Rate反而皆較JL略為輕微。另外ΔVth隨著PBS的VOD偏壓上升會有先往負再往正偏移，並且Id隨stress變化亦由stress後的Vth所主導。推測有兩種機制在互相制衡：(1)斷鍵模型(The broken-bond model) (2)於高電場下之F-N穿隧效應(F-N tunneling)。最後比較JL-GAA-NW以及JL-SG-UTB在不同的過載電壓下之表現，實驗結果很明顯可看出NW的劣化程度較UTB嚴重，歸因為閘極結構關係，NW所受之電場較UTB強而導致劣化程度較為明顯。 最後，綜合以上研究結果，環繞式閘極奈米線無接面電晶體(JL-GAA-NW)在S.S.與PBS的表現上皆優於環繞式閘極奈米線反轉式電晶體(IM-GAA-NW)。

Junctionless transistors are considered as promising architecture to take the place of conventional metal-oxide-silicon field effect transistors (MOSFETs) for continuously scaling down due to the simple fabrication、low thermal budget and better short-channel effect (SCE) immunity. In this research, the electrical characteristics of different channel length、amount of nanowires and process condition on polycrystalline silicon (poly-Si) junctionless and inversion-mode TFTs as well as the reliability of positive gate bias instability (PGB) will be discussed. First of all, the Gate-All-Around nanowire (GAA-NW) configuration which can optimize the gate-control to channel, suppress leakage current and SCE and improve subthreshold swing (S.S.). In this thesis , we had successfully fabricated IM-GAA-NW and JL-GAA-NW devices and discussed with different alignment of gate to drain, different work function of poly-Si Gate (n+ and p+ gate), different channel length, different amount of nanowires and short channel devices：(1) The types of gate alignment either overlay (OV) or align (AL) show no significant differences between JL and IM device. (2) The threshold voltage (Vth), S.S., drain induced barrier lowering (DIBL) and on current (Ion) on p+ gate are worse than on n+ gate due the insufficient of activation of p+ gate. This would be lost the gate controllability on p+ gate devices. (3) The shorter channel length makes less Vth, better S.S. and Ion on both JL and IM device. The performance of S.S. on JL is better than IM while Ion is less than IM device. (4) More amount of nanowires makes higher on current while there is no differences between S.S., Ioff and DIBL. (5) The 60nm short channel devices with stepped structure made by double Spacer Hard Mask (SPHM) process on JL and scaled from the 250nm channel length on mask pattern would get better performance on S.S. and Ion. Next, the Positive Gate Bias Stress Instability (PGBI or PBS) degradation mechanism in IM-GAA-NW, JL-GAA-NW and single gate ultra-thin body Junctionless transistors (JL-SG-UTB) devices with different gate overdrive voltages (VOD) that applied from 1V, 2V, 3V and 4V has been studied systematically with a conventional DC measurement technique. The result shows that there is a Vth shift turning point at PBS with VOD =3V. The degradation rate of Id and Gm on IM device is worse than JL device when we overdrive 3~4V of gate voltages in 1000s. We ascribe that the different carrier transportations of JL and IM may cause the result due to the different electric field in gate oxide and channel. While the degradation rate of Id on IM device is slightly better than JL device when we overdrive 1~2 V of gate voltages in 1000s. ΔVth will first shift negative and then shift positive with the increased VOD. It can be ascribed that there are two mechanisms against each other: (1) The broken-bond model dominated at lower VOD (2) The Fowler-Nordheim tunneling effect (F-N tunneling) dominated at higher VOD. Finally, the device degradation of JL-GAA-NW with different VOD is obviously worse than JL-SG-UTB. We ascribe that there is much higher electric field suffered by NW due to the configuration. Finally, in conclusion, the S.S. and PBS performance of JL-GAA-NW is better than IM-GAA-NW.