完整後設資料紀錄
DC 欄位語言
dc.contributor.author李元勝zh_TW
dc.contributor.author陳巍仁zh_TW
dc.contributor.authorLee, Yuan-Shengen_US
dc.contributor.authorChen, Wei-Zenen_US
dc.date.accessioned2018-01-24T07:41:02Z-
dc.date.available2018-01-24T07:41:02Z-
dc.date.issued2017en_US
dc.identifier.urihttp://etd.lib.nctu.edu.tw/cdrfb3/record/nctu/#GT070250247en_US
dc.identifier.urihttp://hdl.handle.net/11536/141469-
dc.description.abstract本論文提出一個操作在 20Gb/s的光接收機,利用積分取樣式的類比前端接收電路,用以取代傳統高功耗的信號放大器電路,同時整合了鮑率式時脈與資料回復電路,減少了正交相位時脈訊號的使用,大幅減少時脈產生器所需要的功率消耗以及面積,預期可以應用於短距離高密度之光連結系統,如 Optical HDMI、資料中心等高資料頻寬之平台。本晶片使用台積電 40-nm bulk CMOS製程,在資料頻寬 20 Gb/s 以及誤碼率 (BER) 小於10-12時,可達到能量效益 2.4 pJ/bit,靈敏度 -10 dBm,核心電路面積為 0.09mm2。zh_TW
dc.description.abstractThis thesis describes a 20Gbps optical receiver. Integrating type front-end is exploited to replace the conventional power-hungry linear amplifier. Also, it is highly integrated with baud-rate CDR which can reduce power dissipation and hardware complexity of clock distribution network by half. This chip is fabricated in tsmc 40-nm bulk CMOS and achieves an energy efficiency of 2.4 pJ/bit. For bit error rate of less than 10-12, the input sensitivity is -10 dBm. The core circuit area is 0.09 mm2en_US
dc.language.isozh_TWen_US
dc.subject光接收機zh_TW
dc.subject時脈與資料回復電路zh_TW
dc.subjectOptical receiveren_US
dc.subjectClock and data recovery circuiten_US
dc.title一個20Gb/s, 積分型整合鮑率時脈與資料回復電路之光接收機zh_TW
dc.titleA 20Gb/s Integrating Type Optical Receiver with Baud-Rate Clock and Data Recovery Circuiten_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
顯示於類別:畢業論文