标题: | 内建于锁相回路晶片系统之相位杂讯量测技术 Built-in Phase Noise Measurement Technique for on Chip PLL |
作者: | 郭柏毅 陈巍仁 Kuo, Po-I Chen, Wei-Zen 电子工程学系 电子研究所 |
关键字: | 相位杂讯量测;时间数位转换器;差积调变;锁相回路;内建自我测试;Phase Noise Measurement;Time-to-Digital Converter;delta sigma;Phase locked loops;built-in self-test |
公开日期: | 2016 |
摘要: | 相位杂讯是锁相回路系统的一性能指标,一般仅能透过频谱分析仪或示波器量测取得结果,其量测成本昂贵且费时,本论文提出一种相位杂讯量测技术,可整合至单晶片系统中,进行多种锁相回路系统之量测,不需昂贵的仪器设备,同时可降低晶片测试成本。其不同于时脉抖动量测法,本技术可将相位杂讯转为数位讯号,经讯号处理后,可分析杂讯频谱成份及杂讯功率大小,来达到优异的量测结果,其数位讯号亦可以提供给予电路测试及电路校正使用。本晶片可量测最大偏移频率为1 MHz,其可量测最低杂讯功率为-114 dBc/Hz,使用台积电65nm CMOS制程,量测电路操作在1.2 V下,平均功率消耗分别为3 mW,面积为 0.03 mm2。 Phase noise is the key performance indices of phase locked loops. In general, PLLs can be measured using spectrum analyzer or oscilloscope. The equipment and expenses takes too much cost. This thesis propose a phase noise measurement techniques. It can be integrated to SoC, and measure many kinds of PLL system. The phase noise measurement techniques doesn’t use expensive instrument. In other words, testing cost can be reduced. This technique differs from the clock jitter measurement. It convert phase noise to digital signal directly. The composition of noise spectrum and noise power can be analyzed. The digital signal also support circuits to test or calibrate. The measurable maximum offset frequency is 1 MHz. The measurable in band noise floor is -114 dBc/Hz. This work fabricated in 65 nm CMOS technology. Supply voltage is 1.2 volt. The average power consumption of measurement techniques and timing generator is 3 mW. Its area is 0.03 mm2. |
URI: | http://etd.lib.nctu.edu.tw/cdrfb3/record/nctu/#GT070150248 http://hdl.handle.net/11536/141918 |
显示于类别: | Thesis |