內建於鎖相迴路晶片系統之相位雜訊量測技術

Abstract

相位雜訊是鎖相迴路系統的一性能指標，一般僅能透過頻譜分析儀或示波器量測取得結果，其量測成本昂貴且費時，本論文提出一種相位雜訊量測技術，可整合至單晶片系統中，進行多種鎖相迴路系統之量測，不需昂貴的儀器設備，同時可降低晶片測試成本。其不同於時脈抖動量測法，本技術可將相位雜訊轉為數位訊號，經訊號處理後，可分析雜訊頻譜成份及雜訊功率大小，來達到優異的量測結果，其數位訊號亦可以提供給予電路測試及電路校正使用。本晶片可量測最大偏移頻率為1 MHz，其可量測最低雜訊功率為-114 dBc/Hz，使用台積電65nm CMOS製程，量測電路操作在1.2 V下，平均功率消耗分別為3 mW，面積為 0.03 mm2。

Phase noise is the key performance indices of phase locked loops. In general, PLLs can be measured using spectrum analyzer or oscilloscope. The equipment and expenses takes too much cost. This thesis propose a phase noise measurement techniques. It can be integrated to SoC, and measure many kinds of PLL system. The phase noise measurement techniques doesn’t use expensive instrument. In other words, testing cost can be reduced. This technique differs from the clock jitter measurement. It convert phase noise to digital signal directly. The composition of noise spectrum and noise power can be analyzed. The digital signal also support circuits to test or calibrate. The measurable maximum offset frequency is 1 MHz. The measurable in band noise floor is -114 dBc/Hz. This work fabricated in 65 nm CMOS technology. Supply voltage is 1.2 volt. The average power consumption of measurement techniques and timing generator is 3 mW. Its area is 0.03 mm2.