介電質層缺陷相關現象模擬研究

Abstract

近年來，在半導體元件尺寸不斷的微縮下，介電質層缺陷(trap)對於元件的影響越來越無法被忽略。換句話說，因為缺陷的大小只有約幾個埃，因此由介電質缺陷所引起的現象已經小到無法用傳統的機制去模擬而是需要考慮全量子機制。此外，缺陷也十分難以量測他們的位子、狀態與行為，並且由於架構太小導致週期性邊界條件無法滿足，以致傅立葉轉換亦無法在半導體奈米結構下使用。因此當元件為半導體奈米結構時，我們被迫在解決實際空間中具有不明缺陷狀態的量子傳輸問題。因此，我們非常需要在實際空間中精確的量子機制計算，然而這卻會大大的提升計算的負荷。 所以在此篇論文中，我們藉由學習新的物理模型並且由取捨計算時間與計算可靠度的觀點出發來探討缺陷所引起的現象。我們假設此現象是由於電子穿隧到缺陷之中，當外在參數與內在變數改變時，穿隧時間與機率是根據計算實際的穿隧路徑並藉由Fermi’s Golden rule來計算。藉此我們可以討論因缺陷所產生的Random Telegraph Noise (RTN) 和Trap-Assisted Tunneling (TAT) 現象在此篇論文中。

In recent years, the influence of dielectric traps in electron devices have been unavoidably increased as the dimension of electron devices continues scaling down. On the other hand, the size of the traps is about a couple of angstroms, which is so small that a trap-related phenomena is fully quantum-mechanical and impossible to be modeled in terms of classical mechanics. In addition, it is hard for any measurements to detect where traps are, how they are, and what they are. Furthermore, the Fourier transformation, which has been extensively used in the conventional quantum-mechanical treatments, is inapplicable in semiconductor nanostructures, since the size itself is too small to be bulk. Therefore, the periodic boundary condition cannot be validated to well-define the Fourier transformation. We are thus forced to solve quantum mechanical transport problems in semiconductor nanostructures having unidentified traps within a real-space formulation. Therefore, strongly demanded is a real-space computational study which is as precise in terms of quantum-mechanics as possible. However, this substantially increases the computational load. Therefore, the goal of this thesis is to study a physical modelling from the view point of trade-off between computational time and simulation reliability. It is assumed that trap-related phenomena is attributed to tunneling of electrons through traps. The tunneling time and ratio are accordingly calculated with a real-space tunnel path search method and Fermi's Golden rule, while changing external parameters and internal factors in the simulation. As a result, we discuss the phenomenon of Random Telegraph Noise (RTN) and Trap-Assisted Tunneling (TAT), which are attributed to traps in the gate insulation layer.