標題: | 具自我組織架構之WPU Self-Organization Architecture for Wireless Processing Unit |
作者: | 林佑安 許騰尹 Lin, You-An Hsu, Terng-Yin 資訊科學與工程研究所 |
關鍵字: | 自我組織;self-organization |
公開日期: | 2017 |
摘要: | 當今社會中無線通訊蓬勃發展,幾乎每個人都有一台以上的無線通訊裝置,且通訊技術的進化以及大量資料傳輸需求,無線通訊基地台需要處理更多的資料量,再者世界能源正在逐漸減少中,省電也是需要被考量,正因為如此,無線通訊基地台需要一顆可以處理大量資料以及低功率的晶片。我們探討了在同一時間內增加指令處理數量以及省電的方法,並且發現這些方法提升速度效果有限且無法動態分配指令、調整計算單元數量等因素導致擴展性和架構的伸縮彈性不足。
所以,本論文提出一個具自我組織功能之WPU架構,該架構分成指令區塊以及運算區塊。指令區塊存放需要執行的指令地點;運算區塊則擁有自行拿指令、交互溝通之智慧化機制,並且擁有擴充或是減少數量機制,增加架構的擴展性,無需擔心執行能力不足而導致效能降低之問題。並且本論文在LTE-A下的通道估測與等化器之動作模擬該架構的執行是可行的。
除此之外,我們將架構中的多時脈模組加入CEVA DSP作為基礎的平台上驗證模擬模組功能性以及加速前後之效能,發現利用設計的訊號頻率轉換模組讓不同頻率下不同IP皆可傳遞資料以增加單位時間內處理指令的數量並可以減少1.88%至63.85%百分比的時間。 Wireless communication is booming in this era. Almost everyone has more than one wireless communication device. The evolution of communication technology and requirement of a large number of transmission of data. Therefore, wireless communication base station needs to deal with more transmission data. On the other side, the world’s energy is constantly declining, so power saving should be considered. Because of former reason, the wireless communication base station needs the low power chip which can deal with more transmission data. The methods of increasing performance and power saving are discussed. After that, we found these methods have limited efficiency on scalability and flexibility. This paper proposes self-organization architecture for WPU. This structure of this part divides into instruction block and computing block. Instruction block stores the instructions region and computing blocks have self-take instruction, interactive communication of intelligent mechanism and a good expansion mechanism, increasing the scalability of the architecture. We simulate confirmation the architecture feasibility in LTE-A of the channel estimation and the equalizer. In addition, we take the multi-rate clock module add on the CEVA-based platform and simulate verification module functionality and performance. The operation time of the Intellectual Property (IP) on CEVA-based platform reduce 1.88% to 63.85% by using multi-rate clock module and signal frequency converter module. |
URI: | http://etd.lib.nctu.edu.tw/cdrfb3/record/nctu/#GT070356075 http://hdl.handle.net/11536/142247 |
顯示於類別: | 畢業論文 |