具T型閘極與空氣邊襯之新式多晶矽薄膜電晶體

Abstract

在本篇論文中提出一種具T型閘極與空氣邊襯之新式多晶矽薄膜電晶體。我們巧妙的對一以p型多晶矽/n型多晶矽堆疊的雙層薄膜閘極，進行高選擇比的側向蝕刻，將下層n型多晶矽薄膜的兩側朝內蝕刻後便形成了T型閘極。此種新的T型閘製程相當簡單，並且可以順利的加入傳統的電晶體製程。為了更加降低寄生電阻的影響，我們也引入了可實現自我對準的金屬矽化鎳製程。此外，在元件完成並蓋上保護層後，會因為T型閘極的遮蔽效果而在兩側形成空氣邊襯。實驗的結果顯示矽化鎳的T型閘極確實可以大幅降低閘極寄生電阻，而空氣邊襯能夠降低閘極與源/汲極之間的寄生電容。新式的T型閘元件透過側向蝕刻可將通道長度縮短至96奈米，大幅提升了驅動電流與轉導。綜合上述T型閘製程的優點，採用T型閘製程的多晶矽薄膜電晶體其截止頻率相較於採用傳統製程的元件提高了兩倍以上，達到了12.4GHz。較低的閘極寄生電阻也使T型閘元件的最大震盪頻率呈明顯的提升。

In this thesis, a novel poly-Si thin-film transistor (TFT) with T-gate and air spacers is proposed and demonstrated with a new process scheme which ingeniously makes use of a highly selective etching to laterally remove the bottom n+ poly-Si in a p+ poly-Si/n+ poly-Si stack and form the T-gate. This T-gate process is simple and can be readily implemented in conventional fabrication flow. In order to further reduce the parasitic resistances, we also introduce Ni self-aligned silicidation (SALICEDE) process in the fabrication. In addition, owing to the shadowing effect of the T-gate, sidewall air spacers can be obtained after the deposition of the passivation oxide. The results confirm that the silicided T-gate can significantly reduce the parasitic gate resistance, while air spacers can reduce the parasitic capacitances between gate and source/drain (S/D). Furthermore, the lateral etching shortens the channel length of the T-gate devices to 96nm, greatly improving the current drive and transconductance. As a consequence, the cut-off frequency (fT) of the T-gate poly-Si TFTs reaches 12.4GHz, which is two times higher than that of the conventional devices. In the meantime, maximum oscillation frequency (fMAX) also receives a great improvement owing to the reduced gate resistance with the T-gate.